Lines Matching refs:vclk
390 u32 vclk;
1324 u32 vclk; /* in .01 MHz */
1328 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
1331 if (vclk > c.ppll_max)
1332 vclk = c.ppll_max;
1333 if (vclk * 12 < c.ppll_min)
1334 vclk = c.ppll_min/12;
1338 output_freq = post_dividers[i] * vclk;
1353 pll->vclk = vclk;
1357 pll->feedback_divider, vclk, output_freq,
1366 var->pixclock = 100000000 / pll->vclk;
1396 d = pll->vclk * bpp;