Searched refs:pllctrlreg_val (Results 1 - 1 of 1) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/src/shared/
H A Dhndpmu.c4123 * 'pllctrlreg_update': contains info on what entries to use in 'pllctrlreg_val' for the given
4125 * 'pllctrlreg_val' : contains a superset of the BBPLL values to write
4133 const uint32 *pllctrlreg_val)
4160 pllctrlreg_val[indx*pll_ctrlcnt + reg_offset]);
4306 const uint32 *pllctrlreg_val = NULL; local
4346 pllctrlreg_val = pmu1_pllctrl_tab_4335_960mhz;
4351 pllctrlreg_val = pmu1_pllctrl_tab_4335_968mhz;
4355 pllctrlreg_val = pmu1_pllctrl_tab_4335_961mhz;
4358 pllctrlreg_val = pmu1_pllctrl_tab_4335_968mhz;
4374 /* Note: no pllctrlreg_val tabl
4131 si_pmu_pllctrlreg_update(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal, uint8 spur_mode, const pllctrl_data_t *pllctrlreg_update, uint32 array_size, const uint32 *pllctrlreg_val) argument
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