Lines Matching refs:pllctrlreg_val
4123 * 'pllctrlreg_update': contains info on what entries to use in 'pllctrlreg_val' for the given
4125 * 'pllctrlreg_val' : contains a superset of the BBPLL values to write
4133 const uint32 *pllctrlreg_val)
4160 pllctrlreg_val[indx*pll_ctrlcnt + reg_offset]);
4306 const uint32 *pllctrlreg_val = NULL;
4346 pllctrlreg_val = pmu1_pllctrl_tab_4335_960mhz;
4351 pllctrlreg_val = pmu1_pllctrl_tab_4335_968mhz;
4355 pllctrlreg_val = pmu1_pllctrl_tab_4335_961mhz;
4358 pllctrlreg_val = pmu1_pllctrl_tab_4335_968mhz;
4374 /* Note: no pllctrlreg_val table, because the PLL ctrl regs are calculated */
4400 pllctrlreg_val = pmu1_pllctrl_tab_4350C0_963mhz;
4403 pllctrlreg_val = pmu1_pllctrl_tab_4350C0_963mhz;
4405 pllctrlreg_val = pmu1_pllctrl_tab_4350_963mhz;
4428 pllctrlreg_val = pmu1_pllctrl_tab_43242A0;
4430 pllctrlreg_val = pmu1_pllctrl_tab_43242A1;
4462 array_size, pllctrlreg_val);
4485 if (pllctrlreg_val) {
4487 pllctrlreg_val);