Searched refs:pll0 (Results 1 - 3 of 3) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/plat-samsung/include/plat/
H A Dpll6553x.h27 u32 pll0, u32 pll1)
33 mdiv = (pll0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK;
34 pdiv = (pll0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK;
35 sdiv = (pll0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK;
26 s3c_get_pll6553x(unsigned long baseclk, u32 pll0, u32 pll1) argument
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/avr32/mach-at32ap/
H A Dat32ap700x.c311 static struct clk pll0 = { variable in typeref:struct:clk
312 .name = "pll0",
326 * The main clock can be either osc0 or pll0. The boot loader may
574 else if (parent == &osc0 || parent == &pll0)
579 if (parent == &pll0 || parent == &pll1)
601 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
1512 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1513 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
2200 &pll0,
2267 main_clock = &pll0;
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/netgear-R7000-V1.0.7.12_1.2.5/src/shared/
H A Dhndpmu.c4991 uint32 freq_tgt, pll0; local
5011 pll0 = R_REG(osh, PMUREG(sih, pllcontrol_data));
5013 freq_tgt = (pll0 & PMU15_PLL_PC0_FREQTGT_MASK) >> PMU15_PLL_PC0_FREQTGT_SHIFT;
5043 pll0 = (pll0 & ~PMU15_PLL_PC0_FREQTGT_MASK) | (xt->freq_tgt << PMU15_PLL_PC0_FREQTGT_SHIFT);
5044 W_REG(osh, PMUREG(sih, pllcontrol_data), pll0);
5074 uint32 freq_tgt = 0, pll0 = 0; local
5083 pll0 = R_REG(osh, PMUREG(sih, pllcontrol_data));
5084 freq_tgt = (pll0 & PMU15_PLL_PC0_FREQTGT_MASK) >> PMU15_PLL_PC0_FREQTGT_SHIFT;
5112 uint32 freq_tgt, pll0; local
6111 si_pmu5_clock(si_t *sih, osl_t *osh, chipcregs_t *cc, uint pll0, uint m) argument
6163 si_4706_pmu_clock(si_t *sih, osl_t *osh, chipcregs_t *cc, uint pll0, uint m) argument
7637 uint32 pll0; local
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