Lines Matching refs:pll0
4991 uint32 freq_tgt, pll0;
5011 pll0 = R_REG(osh, PMUREG(sih, pllcontrol_data));
5013 freq_tgt = (pll0 & PMU15_PLL_PC0_FREQTGT_MASK) >> PMU15_PLL_PC0_FREQTGT_SHIFT;
5043 pll0 = (pll0 & ~PMU15_PLL_PC0_FREQTGT_MASK) | (xt->freq_tgt << PMU15_PLL_PC0_FREQTGT_SHIFT);
5044 W_REG(osh, PMUREG(sih, pllcontrol_data), pll0);
5074 uint32 freq_tgt = 0, pll0 = 0;
5083 pll0 = R_REG(osh, PMUREG(sih, pllcontrol_data));
5084 freq_tgt = (pll0 & PMU15_PLL_PC0_FREQTGT_MASK) >> PMU15_PLL_PC0_FREQTGT_SHIFT;
5112 uint32 freq_tgt, pll0;
5115 pll0 = R_REG(osh, PMUREG(sih, pllcontrol_data));
5117 freq_tgt = (pll0 & PMU15_PLL_PC0_FREQTGT_MASK) >> PMU15_PLL_PC0_FREQTGT_SHIFT;
6108 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
6111 BCMINITFN(si_pmu5_clock)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint pll0, uint m)
6115 if ((pll0 & 3) || (pll0 > PMU4716_MAINPLL_PLL0)) {
6116 PMU_ERROR(("%s: Bad pll0: %d\n", __FUNCTION__, pll0));
6135 W_REG(osh, PMUREG(sih, pllcontrol_addr), pll0 + PMU5_PLL_P1P2_OFF);
6141 W_REG(osh, PMUREG(sih, pllcontrol_addr), pll0 + PMU5_PLL_M14_OFF);
6146 W_REG(osh, PMUREG(sih, pllcontrol_addr), pll0 + PMU5_PLL_NM5_OFF);
6163 BCMINITFN(si_4706_pmu_clock)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint pll0, uint m)
6175 W_REG(osh, PMUREG(sih, pllcontrol_addr), pll0 + PMU6_4706_PROCPLL_OFF);
7637 uint32 pll0;
7645 pll0 = R_REG(osh, pllctrl_data);
7646 pll0 &= ~PMU15_PLL_PC0_FREQTGT_MASK;
7647 pll0 |= (xt->freq_tgt << PMU15_PLL_PC0_FREQTGT_SHIFT);
7648 W_REG(osh, pllctrl_data, pll0);