Searched refs:pPLLReg (Results 1 - 2 of 2) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-bcmring/csp/chipc/
H A DchipcHw.c64 volatile uint32_t *pPLLReg = (uint32_t *) 0x0; local
100 pPLLReg = &pChipcHw->DDRClock;
104 pPLLReg = &pChipcHw->ARMClock;
108 pPLLReg = &pChipcHw->ESWClock;
112 pPLLReg = &pChipcHw->VPMClock;
116 pPLLReg = &pChipcHw->ESW125Clock;
120 pPLLReg = &pChipcHw->UARTClock;
124 pPLLReg = &pChipcHw->SDIO0Clock;
128 pPLLReg = &pChipcHw->SDIO1Clock;
132 pPLLReg
264 volatile uint32_t *pPLLReg = (uint32_t *) 0x0; local
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-bcmring/include/mach/csp/
H A DchipcHw_inline.h844 volatile uint32_t *pPLLReg = (uint32_t *) 0x0; local
849 pPLLReg = &pChipcHw->DDRClock;
852 pPLLReg = &pChipcHw->ARMClock;
855 pPLLReg = &pChipcHw->ESWClock;
858 pPLLReg = &pChipcHw->VPMClock;
861 pPLLReg = &pChipcHw->ESW125Clock;
864 pPLLReg = &pChipcHw->UARTClock;
867 pPLLReg = &pChipcHw->SDIO0Clock;
870 pPLLReg = &pChipcHw->SDIO1Clock;
873 pPLLReg
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