Lines Matching refs:pPLLReg
64 volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
100 pPLLReg = &pChipcHw->DDRClock;
104 pPLLReg = &pChipcHw->ARMClock;
108 pPLLReg = &pChipcHw->ESWClock;
112 pPLLReg = &pChipcHw->VPMClock;
116 pPLLReg = &pChipcHw->ESW125Clock;
120 pPLLReg = &pChipcHw->UARTClock;
124 pPLLReg = &pChipcHw->SDIO0Clock;
128 pPLLReg = &pChipcHw->SDIO1Clock;
132 pPLLReg = &pChipcHw->SPIClock;
136 pPLLReg = &pChipcHw->ETMClock;
140 pPLLReg = &pChipcHw->USBClock;
144 pPLLReg = &pChipcHw->LCDClock;
148 pPLLReg = &pChipcHw->APMClock;
188 if (pPLLReg) {
190 if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
198 if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
202 return chipcHw_divide(vcoHz, ((*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
264 volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
314 pPLLReg = &pChipcHw->DDRClock;
319 pPLLReg = &pChipcHw->ARMClock;
324 pPLLReg = &pChipcHw->ESWClock;
336 pPLLReg = &pChipcHw->VPMClock;
341 pPLLReg = &pChipcHw->ESW125Clock;
346 pPLLReg = &pChipcHw->UARTClock;
351 pPLLReg = &pChipcHw->SDIO0Clock;
356 pPLLReg = &pChipcHw->SDIO1Clock;
361 pPLLReg = &pChipcHw->SPIClock;
366 pPLLReg = &pChipcHw->ETMClock;
371 pPLLReg = &pChipcHw->USBClock;
376 pPLLReg = &pChipcHw->LCDClock;
381 pPLLReg = &pChipcHw->APMClock;
424 if (pPLLReg) {
426 reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_SOURCE_GPIO);
427 reg32_modify_or(pPLLReg, chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
429 if (pPLLReg == &pChipcHw->DDRClock) {
436 if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
441 reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK));
442 reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq));
444 freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
449 reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);