Searched refs:p15 (Results 1 - 25 of 163) sorted by relevance

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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-msm/
H A Didle.S8 mrc p15, 0, r1, c1, c0, 0 /* read current CR */
11 mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */
14 mcr p15, 0, r0, c7, c10, 0 /* flush the cache */
15 mcr p15, 0, r0, c7, c10, 4 /* memory barrier */
16 mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */
18 mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mm/
H A Dpabort-v7.S17 mrc p15, 0, r0, c6, c0, 2 @ get IFAR
18 mrc p15, 0, r1, c5, c0, 1 @ get IFSR
H A Dproc-fa526.S42 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
45 mcr p15, 0, r0, c1, c0, 0 @ disable caches
63 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
64 mcr p15, 0, ip, c7, c10, 4 @ drain WB
66 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
68 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
72 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
82 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
87 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
91 mcr p15,
[all...]
H A Dtlb-fa.S42 mcr p15, 0, r3, c7, c10, 4 @ drain WB
45 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
49 mcr p15, 0, r3, c7, c5, 6 @ invalidate BTB
50 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
56 mcr p15, 0, r3, c7, c10, 4 @ drain WB
59 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
63 mcr p15, 0, r3, c7, c5, 6 @ invalidate BTB
64 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
65 mcr p15, 0, r3, c7, c5, 4 @ prefetch flush
H A Dproc-arm940.S40 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
43 mcr p15, 0, r0, c1, c0, 0 @ disable caches
53 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
54 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
55 mcr p15, 0, ip, c7, c10, 4 @ drain WB
56 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
59 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
67 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
98 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
102 2: mcr p15,
[all...]
H A Dcache-fa.S56 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
58 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
59 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
60 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
61 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
81 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
82 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
87 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
88 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
89 mcrne p15,
[all...]
H A Dproc-mohawk.S54 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
74 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
75 mcr p15, 0, ip, c7, c10, 4 @ drain WB
76 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
77 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
80 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
91 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
92 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
113 mcr p15,
[all...]
H A Dpabort-v6.S17 mrc p15, 0, r1, c5, c0, 1 @ get IFSR
H A Dproc-arm920.S72 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
75 mcr p15, 0, r0, c1, c0, 0 @ disable caches
90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
91 mcr p15, 0, ip, c7, c10, 4 @ drain WB
93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
95 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
98 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
138 mcrne p15,
[all...]
H A Dproc-arm922.S74 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
77 mcr p15, 0, r0, c1, c0, 0 @ disable caches
92 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
93 mcr p15, 0, ip, c7, c10, 4 @ drain WB
95 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
97 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
100 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
140 mcrne p15,
[all...]
H A Dproc-arm1020e.S82 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
100 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
101 mcr p15, 0, ip, c7, c10, 4 @ drain WB
103 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
105 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
108 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
116 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
140 mcr p15, 0, ip, c7, c10, 4 @ drain WB
143 2: mcr p15,
[all...]
H A Dproc-arm1026.S71 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
74 mcr p15, 0, r0, c1, c0, 0 @ disable caches
89 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
90 mcr p15, 0, ip, c7, c10, 4 @ drain WB
92 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
94 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
97 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
105 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
129 1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
134 mcrne p15,
[all...]
H A Dproc-arm1020.S82 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
100 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
101 mcr p15, 0, ip, c7, c10, 4 @ drain WB
103 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
105 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
108 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
116 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
140 mcr p15, 0, ip, c7, c10, 4 @ drain WB
143 2: mcr p15,
[all...]
H A Dproc-arm925.S46 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
49 mcr p15, 0, r0, c1, c0, 0 @ disable caches
71 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
72 mcr p15, 0, ip, c7, c10, 4 @ drain WB
74 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
76 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
79 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
90 mrc p15, 0, r1, c1, c0, 0 @ Read control register
91 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
93 mcr p15,
[all...]
H A Dproc-arm926.S64 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
67 mcr p15, 0, r0, c1, c0, 0 @ disable caches
82 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
83 mcr p15, 0, ip, c7, c10, 4 @ drain WB
85 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
87 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
90 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
101 mrc p15, 0, r1, c1, c0, 0 @ Read control register
102 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
107 mcr p15,
[all...]
H A Dproc-arm946.S47 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
50 mcr p15, 0, r0, c1, c0, 0 @ disable caches
60 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
61 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
62 mcr p15, 0, ip, c7, c10, 4 @ drain WB
63 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
66 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
74 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
93 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
97 2: mcr p15,
[all...]
H A Dproc-arm1022.S71 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
74 mcr p15, 0, r0, c1, c0, 0 @ disable caches
89 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
90 mcr p15, 0, ip, c7, c10, 4 @ drain WB
92 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
94 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
97 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
105 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
131 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
139 mcrne p15,
[all...]
H A Dproc-sa110.S40 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
48 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
49 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
52 mcr p15, 0, r0, c1, c0, 0 @ disable caches
67 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
68 mcr p15, 0, ip, c7, c10, 4 @ drain WB
70 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
72 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
75 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
92 mcr p15,
[all...]
H A Dcache-v6.S29 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
30 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
31 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
32 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
50 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
52 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
57 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
120 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line
128 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
130 mcr p15,
[all...]
H A Dtlb-v6.S39 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
48 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
50 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
52 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
57 mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB
58 mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier
71 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
78 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
79 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
81 mcr p15,
[all...]
H A Dproc-xsc3.S60 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
72 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
93 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
96 mcr p15, 0, r0, c1, c0, 0 @ disable caches
112 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
118 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
163 mcrne p15,
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/boot/compressed/
H A Dbig-endian.S10 mrc p15, 0, r0, c1, c0, 0 @ read control reg
12 mcr p15, 0, r0, c1, c0, 0 @ write control reg
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s3c64xx/
H A Dsleep.S41 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
42 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
43 mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
44 mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
45 mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control
46 mrc p15, 0, r9, c1, c0, 0 @ Control register
47 mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
48 mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls
118 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
119 mcr p15,
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-iop32x/include/mach/
H A Dentry-macro.S16 mrc p15, 0, \tmp, c15, c1, 0
18 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
19 mrc p15, 0, \tmp, c15, c1, 0
32 mrc p15, 0, \tmp1, c15, c1, 0
35 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-iop33x/include/mach/
H A Dentry-macro.S16 mrc p15, 0, \tmp, c15, c1, 0
18 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
19 mrc p15, 0, \tmp, c15, c1, 0
33 mrc p15, 0, \tmp1, c15, c1, 0
36 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access

Completed in 74 milliseconds

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