Lines Matching refs:p15
60 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
72 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
93 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
96 mcr p15, 0, r0, c1, c0, 0 @ disable caches
112 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
118 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
163 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
164 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
165 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
186 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
187 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
192 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
193 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
194 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
214 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
219 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
220 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
221 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
235 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
240 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
241 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
242 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
259 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
261 mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D line
262 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line
266 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
279 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
283 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
296 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
300 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
339 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
357 mcr p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
358 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
359 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
361 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
362 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
413 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
414 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
415 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
416 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
418 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
421 mcr p15, 0, r0, c15, c1, 0 @ write CP access register
423 mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg
426 mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
432 mrc p15, 1, r0, c0, c0, 1 @ get L2 present information
437 mrc p15, 0, r0, c1, c0, 0 @ get control register