Searched refs:ath5k_hw_reg_read (Results 1 - 13 of 13) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/net/wireless/ath/ath5k/
H A Ddma.c52 ath5k_hw_reg_read(ah, AR5K_CR);
70 (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0;
84 return ath5k_hw_reg_read(ah, AR5K_RXDP);
123 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
147 ath5k_hw_reg_read(ah, AR5K_CR);
183 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
203 ath5k_hw_reg_read(ah, AR5K_CR);
212 pending = ath5k_hw_reg_read(ah,
231 AR5K_REG_SM(ath5k_hw_reg_read(ah,
248 pending = ath5k_hw_reg_read(a
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H A Dgpio.c87 (ath5k_hw_reg_read(ah, AR5K_GPIOCR) & ~AR5K_GPIOCR_OUT(gpio))
102 (ath5k_hw_reg_read(ah, AR5K_GPIOCR) & ~AR5K_GPIOCR_OUT(gpio))
117 return ((ath5k_hw_reg_read(ah, AR5K_GPIODI) & AR5K_GPIODI_M) >> gpio) &
132 data = ath5k_hw_reg_read(ah, AR5K_GPIODO);
156 data = (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &
H A Dani.c369 as->pfc_cycles = ath5k_hw_reg_read(ah, AR5K_PROFCNT_CYCLE);
370 as->pfc_busy = ath5k_hw_reg_read(ah, AR5K_PROFCNT_RXCLR);
371 as->pfc_tx = ath5k_hw_reg_read(ah, AR5K_PROFCNT_TX);
372 as->pfc_rx = ath5k_hw_reg_read(ah, AR5K_PROFCNT_RX);
410 ofdm_err = ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT1);
411 cck_err = ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT2);
709 ath5k_hw_reg_read(ah, AR5K_ACK_FAIL));
711 ath5k_hw_reg_read(ah, AR5K_RTS_FAIL));
713 ath5k_hw_reg_read(ah, AR5K_RTS_OK));
715 ath5k_hw_reg_read(a
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H A Dpcu.c54 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
129 stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
130 stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
131 stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
132 stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
133 stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
299 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
420 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
424 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
512 tsf_upper1 = ath5k_hw_reg_read(a
[all...]
H A Dreset.c45 data = ath5k_hw_reg_read(ah, reg);
205 ath5k_hw_reg_read(ah, AR5K_RXDP);
247 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
278 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
295 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
506 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
674 if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc)
699 usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
937 s_seq[i] = ath5k_hw_reg_read(ah,
941 s_seq[0] = ath5k_hw_reg_read(a
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H A Dattach.c54 init_val = ath5k_hw_reg_read(ah, cur_reg);
59 cur_val = ath5k_hw_reg_read(ah, cur_reg);
74 cur_val = ath5k_hw_reg_read(ah, cur_reg);
134 srev = ath5k_hw_reg_read(ah, AR5K_SREV);
155 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
H A Ddebug.c165 ath5k_hw_reg_read(sc->ah, r->addr));
209 v = ath5k_hw_reg_read(sc->ah, AR5K_BEACON);
216 "AR5K_LAST_TSTP", ath5k_hw_reg_read(sc->ah, AR5K_LAST_TSTP));
219 "AR5K_BEACON_CNT", ath5k_hw_reg_read(sc->ah, AR5K_BEACON_CNT));
221 v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER0);
225 v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER1);
229 v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER2);
233 v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER3);
402 v = ath5k_hw_reg_read(sc->ah, AR5K_DEFAULT_ANTENNA);
406 v = ath5k_hw_reg_read(s
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H A Dath5k.h115 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
119 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
123 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
126 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
130 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
137 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
1308 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) function
H A Dqcu.c156 pending = ath5k_hw_reg_read(ah, AR5K_QUEUE_STATUS(queue));
235 (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
237 (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
H A Dphy.c382 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
1104 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1166 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
1207 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M;
1251 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1279 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1280 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1281 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1346 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
1351 iq_corr = ath5k_hw_reg_read(a
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H A Deeprom.c43 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
51 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
55 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
H A Dinitvals.c1385 ath5k_hw_reg_read(ah, ini_regs[i].ini_register);
H A Dbase.c455 return ath5k_hw_reg_read(ah, reg_offset);

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