1/* 2 * Copyright (C) 2010 Bruno Randolf <br1@einfach.org> 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "ath5k.h" 18#include "base.h" 19#include "reg.h" 20#include "debug.h" 21#include "ani.h" 22 23/** 24 * DOC: Basic ANI Operation 25 * 26 * Adaptive Noise Immunity (ANI) controls five noise immunity parameters 27 * depending on the amount of interference in the environment, increasing 28 * or reducing sensitivity as necessary. 29 * 30 * The parameters are: 31 * - "noise immunity" 32 * - "spur immunity" 33 * - "firstep level" 34 * - "OFDM weak signal detection" 35 * - "CCK weak signal detection" 36 * 37 * Basically we look at the amount of ODFM and CCK timing errors we get and then 38 * raise or lower immunity accordingly by setting one or more of these 39 * parameters. 40 * Newer chipsets have PHY error counters in hardware which will generate a MIB 41 * interrupt when they overflow. Older hardware has too enable PHY error frames 42 * by setting a RX flag and then count every single PHY error. When a specified 43 * threshold of errors has been reached we will raise immunity. 44 * Also we regularly check the amount of errors and lower or raise immunity as 45 * necessary. 46 */ 47 48 49/*** ANI parameter control ***/ 50 51/** 52 * ath5k_ani_set_noise_immunity_level() - Set noise immunity level 53 * 54 * @level: level between 0 and @ATH5K_ANI_MAX_NOISE_IMM_LVL 55 */ 56void 57ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level) 58{ 59 /* TODO: 60 * ANI documents suggest the following five levels to use, but the HAL 61 * and ath9k use only use the last two levels, making this 62 * essentially an on/off option. There *may* be a reason for this (???), 63 * so i stick with the HAL version for now... 64 */ 65 const s8 sz[] = { -55, -62 }; 66 const s8 lo[] = { -64, -70 }; 67 const s8 hi[] = { -14, -12 }; 68 const s8 fr[] = { -78, -80 }; 69 if (level < 0 || level >= ARRAY_SIZE(sz)) { 70 ATH5K_ERR(ah->ah_sc, "noise immuniy level %d out of range", 71 level); 72 return; 73 } 74 75 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, 76 AR5K_PHY_DESIRED_SIZE_TOT, sz[level]); 77 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_AGCCOARSE, 78 AR5K_PHY_AGCCOARSE_LO, lo[level]); 79 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_AGCCOARSE, 80 AR5K_PHY_AGCCOARSE_HI, hi[level]); 81 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG, 82 AR5K_PHY_SIG_FIRPWR, fr[level]); 83 84 ah->ah_sc->ani_state.noise_imm_level = level; 85 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "new level %d", level); 86} 87 88 89/** 90 * ath5k_ani_set_spur_immunity_level() - Set spur immunity level 91 * 92 * @level: level between 0 and @max_spur_level (the maximum level is dependent 93 * on the chip revision). 94 */ 95void 96ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level) 97{ 98 const int val[] = { 2, 4, 6, 8, 10, 12, 14, 16 }; 99 100 if (level < 0 || level >= ARRAY_SIZE(val) || 101 level > ah->ah_sc->ani_state.max_spur_level) { 102 ATH5K_ERR(ah->ah_sc, "spur immunity level %d out of range", 103 level); 104 return; 105 } 106 107 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR, 108 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, val[level]); 109 110 ah->ah_sc->ani_state.spur_level = level; 111 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "new level %d", level); 112} 113 114 115/** 116 * ath5k_ani_set_firstep_level() - Set "firstep" level 117 * 118 * @level: level between 0 and @ATH5K_ANI_MAX_FIRSTEP_LVL 119 */ 120void 121ath5k_ani_set_firstep_level(struct ath5k_hw *ah, int level) 122{ 123 const int val[] = { 0, 4, 8 }; 124 125 if (level < 0 || level >= ARRAY_SIZE(val)) { 126 ATH5K_ERR(ah->ah_sc, "firstep level %d out of range", level); 127 return; 128 } 129 130 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG, 131 AR5K_PHY_SIG_FIRSTEP, val[level]); 132 133 ah->ah_sc->ani_state.firstep_level = level; 134 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "new level %d", level); 135} 136 137 138/** 139 * ath5k_ani_set_ofdm_weak_signal_detection() - Control OFDM weak signal 140 * detection 141 * 142 * @on: turn on or off 143 */ 144void 145ath5k_ani_set_ofdm_weak_signal_detection(struct ath5k_hw *ah, bool on) 146{ 147 const int m1l[] = { 127, 50 }; 148 const int m2l[] = { 127, 40 }; 149 const int m1[] = { 127, 0x4d }; 150 const int m2[] = { 127, 0x40 }; 151 const int m2cnt[] = { 31, 16 }; 152 const int m2lcnt[] = { 63, 48 }; 153 154 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR, 155 AR5K_PHY_WEAK_OFDM_LOW_THR_M1, m1l[on]); 156 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR, 157 AR5K_PHY_WEAK_OFDM_LOW_THR_M2, m2l[on]); 158 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_HIGH_THR, 159 AR5K_PHY_WEAK_OFDM_HIGH_THR_M1, m1[on]); 160 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_HIGH_THR, 161 AR5K_PHY_WEAK_OFDM_HIGH_THR_M2, m2[on]); 162 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_HIGH_THR, 163 AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT, m2cnt[on]); 164 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR, 165 AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT, m2lcnt[on]); 166 167 if (on) 168 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR, 169 AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN); 170 else 171 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR, 172 AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN); 173 174 ah->ah_sc->ani_state.ofdm_weak_sig = on; 175 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "turned %s", 176 on ? "on" : "off"); 177} 178 179 180/** 181 * ath5k_ani_set_cck_weak_signal_detection() - control CCK weak signal detection 182 * 183 * @on: turn on or off 184 */ 185void 186ath5k_ani_set_cck_weak_signal_detection(struct ath5k_hw *ah, bool on) 187{ 188 const int val[] = { 8, 6 }; 189 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_CCK_CROSSCORR, 190 AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR, val[on]); 191 ah->ah_sc->ani_state.cck_weak_sig = on; 192 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "turned %s", 193 on ? "on" : "off"); 194} 195 196 197/*** ANI algorithm ***/ 198 199/** 200 * ath5k_ani_raise_immunity() - Increase noise immunity 201 * 202 * @ofdm_trigger: If this is true we are called because of too many OFDM errors, 203 * the algorithm will tune more parameters then. 204 * 205 * Try to raise noise immunity (=decrease sensitivity) in several steps 206 * depending on the average RSSI of the beacons we received. 207 */ 208static void 209ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as, 210 bool ofdm_trigger) 211{ 212 int rssi = ah->ah_beacon_rssi_avg.avg; 213 214 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "raise immunity (%s)", 215 ofdm_trigger ? "ODFM" : "CCK"); 216 217 /* first: raise noise immunity */ 218 if (as->noise_imm_level < ATH5K_ANI_MAX_NOISE_IMM_LVL) { 219 ath5k_ani_set_noise_immunity_level(ah, as->noise_imm_level + 1); 220 return; 221 } 222 223 /* only OFDM: raise spur immunity level */ 224 if (ofdm_trigger && 225 as->spur_level < ah->ah_sc->ani_state.max_spur_level) { 226 ath5k_ani_set_spur_immunity_level(ah, as->spur_level + 1); 227 return; 228 } 229 230 /* AP mode */ 231 if (ah->ah_sc->opmode == NL80211_IFTYPE_AP) { 232 if (as->firstep_level < ATH5K_ANI_MAX_FIRSTEP_LVL) 233 ath5k_ani_set_firstep_level(ah, as->firstep_level + 1); 234 return; 235 } 236 237 /* STA and IBSS mode */ 238 239 /* TODO: for IBSS mode it would be better to keep a beacon RSSI average 240 * per each neighbour node and use the minimum of these, to make sure we 241 * don't shut out a remote node by raising immunity too high. */ 242 243 if (rssi > ATH5K_ANI_RSSI_THR_HIGH) { 244 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 245 "beacon RSSI high"); 246 /* only OFDM: beacon RSSI is high, we can disable ODFM weak 247 * signal detection */ 248 if (ofdm_trigger && as->ofdm_weak_sig == true) { 249 ath5k_ani_set_ofdm_weak_signal_detection(ah, false); 250 ath5k_ani_set_spur_immunity_level(ah, 0); 251 return; 252 } 253 /* as a last resort or CCK: raise firstep level */ 254 if (as->firstep_level < ATH5K_ANI_MAX_FIRSTEP_LVL) { 255 ath5k_ani_set_firstep_level(ah, as->firstep_level + 1); 256 return; 257 } 258 } else if (rssi > ATH5K_ANI_RSSI_THR_LOW) { 259 /* beacon RSSI in mid range, we need OFDM weak signal detect, 260 * but can raise firstep level */ 261 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 262 "beacon RSSI mid"); 263 if (ofdm_trigger && as->ofdm_weak_sig == false) 264 ath5k_ani_set_ofdm_weak_signal_detection(ah, true); 265 if (as->firstep_level < ATH5K_ANI_MAX_FIRSTEP_LVL) 266 ath5k_ani_set_firstep_level(ah, as->firstep_level + 1); 267 return; 268 } else if (ah->ah_current_channel->band == IEEE80211_BAND_2GHZ) { 269 /* beacon RSSI is low. in B/G mode turn of OFDM weak signal 270 * detect and zero firstep level to maximize CCK sensitivity */ 271 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 272 "beacon RSSI low, 2GHz"); 273 if (ofdm_trigger && as->ofdm_weak_sig == true) 274 ath5k_ani_set_ofdm_weak_signal_detection(ah, false); 275 if (as->firstep_level > 0) 276 ath5k_ani_set_firstep_level(ah, 0); 277 return; 278 } 279 280 /* TODO: why not?: 281 if (as->cck_weak_sig == true) { 282 ath5k_ani_set_cck_weak_signal_detection(ah, false); 283 } 284 */ 285} 286 287 288/** 289 * ath5k_ani_lower_immunity() - Decrease noise immunity 290 * 291 * Try to lower noise immunity (=increase sensitivity) in several steps 292 * depending on the average RSSI of the beacons we received. 293 */ 294static void 295ath5k_ani_lower_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as) 296{ 297 int rssi = ah->ah_beacon_rssi_avg.avg; 298 299 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "lower immunity"); 300 301 if (ah->ah_sc->opmode == NL80211_IFTYPE_AP) { 302 /* AP mode */ 303 if (as->firstep_level > 0) { 304 ath5k_ani_set_firstep_level(ah, as->firstep_level - 1); 305 return; 306 } 307 } else { 308 /* STA and IBSS mode (see TODO above) */ 309 if (rssi > ATH5K_ANI_RSSI_THR_HIGH) { 310 /* beacon signal is high, leave OFDM weak signal 311 * detection off or it may oscillate 312 * TODO: who said it's off??? */ 313 } else if (rssi > ATH5K_ANI_RSSI_THR_LOW) { 314 /* beacon RSSI is mid-range: turn on ODFM weak signal 315 * detection and next, lower firstep level */ 316 if (as->ofdm_weak_sig == false) { 317 ath5k_ani_set_ofdm_weak_signal_detection(ah, 318 true); 319 return; 320 } 321 if (as->firstep_level > 0) { 322 ath5k_ani_set_firstep_level(ah, 323 as->firstep_level - 1); 324 return; 325 } 326 } else { 327 /* beacon signal is low: only reduce firstep level */ 328 if (as->firstep_level > 0) { 329 ath5k_ani_set_firstep_level(ah, 330 as->firstep_level - 1); 331 return; 332 } 333 } 334 } 335 336 /* all modes */ 337 if (as->spur_level > 0) { 338 ath5k_ani_set_spur_immunity_level(ah, as->spur_level - 1); 339 return; 340 } 341 342 /* finally, reduce noise immunity */ 343 if (as->noise_imm_level > 0) { 344 ath5k_ani_set_noise_immunity_level(ah, as->noise_imm_level - 1); 345 return; 346 } 347} 348 349 350/** 351 * ath5k_hw_ani_get_listen_time() - Calculate time spent listening 352 * 353 * Return an approximation of the time spent "listening" in milliseconds (ms) 354 * since the last call of this function by deducting the cycles spent 355 * transmitting and receiving from the total cycle count. 356 * Save profile count values for debugging/statistics and because we might want 357 * to use them later. 358 * 359 * We assume no one else clears these registers! 360 */ 361static int 362ath5k_hw_ani_get_listen_time(struct ath5k_hw *ah, struct ath5k_ani_state *as) 363{ 364 int listen; 365 366 /* freeze */ 367 ath5k_hw_reg_write(ah, AR5K_MIBC_FMC, AR5K_MIBC); 368 /* read */ 369 as->pfc_cycles = ath5k_hw_reg_read(ah, AR5K_PROFCNT_CYCLE); 370 as->pfc_busy = ath5k_hw_reg_read(ah, AR5K_PROFCNT_RXCLR); 371 as->pfc_tx = ath5k_hw_reg_read(ah, AR5K_PROFCNT_TX); 372 as->pfc_rx = ath5k_hw_reg_read(ah, AR5K_PROFCNT_RX); 373 /* clear */ 374 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_TX); 375 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RX); 376 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RXCLR); 377 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_CYCLE); 378 /* un-freeze */ 379 ath5k_hw_reg_write(ah, 0, AR5K_MIBC); 380 381 /* TODO: where does 44000 come from? (11g clock rate?) */ 382 listen = (as->pfc_cycles - as->pfc_rx - as->pfc_tx) / 44000; 383 384 if (as->pfc_cycles == 0 || listen < 0) 385 return 0; 386 return listen; 387} 388 389 390/** 391 * ath5k_ani_save_and_clear_phy_errors() - Clear and save PHY error counters 392 * 393 * Clear the PHY error counters as soon as possible, since this might be called 394 * from a MIB interrupt and we want to make sure we don't get interrupted again. 395 * Add the count of CCK and OFDM errors to our internal state, so it can be used 396 * by the algorithm later. 397 * 398 * Will be called from interrupt and tasklet context. 399 * Returns 0 if both counters are zero. 400 */ 401static int 402ath5k_ani_save_and_clear_phy_errors(struct ath5k_hw *ah, 403 struct ath5k_ani_state *as) 404{ 405 unsigned int ofdm_err, cck_err; 406 407 if (!ah->ah_capabilities.cap_has_phyerr_counters) 408 return 0; 409 410 ofdm_err = ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT1); 411 cck_err = ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT2); 412 413 /* reset counters first, we might be in a hurry (interrupt) */ 414 ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_OFDM_TRIG_HIGH, 415 AR5K_PHYERR_CNT1); 416 ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_CCK_TRIG_HIGH, 417 AR5K_PHYERR_CNT2); 418 419 ofdm_err = ATH5K_ANI_OFDM_TRIG_HIGH - (ATH5K_PHYERR_CNT_MAX - ofdm_err); 420 cck_err = ATH5K_ANI_CCK_TRIG_HIGH - (ATH5K_PHYERR_CNT_MAX - cck_err); 421 422 /* sometimes both can be zero, especially when there is a superfluous 423 * second interrupt. detect that here and return an error. */ 424 if (ofdm_err <= 0 && cck_err <= 0) 425 return 0; 426 427 /* avoid negative values should one of the registers overflow */ 428 if (ofdm_err > 0) { 429 as->ofdm_errors += ofdm_err; 430 as->sum_ofdm_errors += ofdm_err; 431 } 432 if (cck_err > 0) { 433 as->cck_errors += cck_err; 434 as->sum_cck_errors += cck_err; 435 } 436 return 1; 437} 438 439 440/** 441 * ath5k_ani_period_restart() - Restart ANI period 442 * 443 * Just reset counters, so they are clear for the next "ani period". 444 */ 445static void 446ath5k_ani_period_restart(struct ath5k_hw *ah, struct ath5k_ani_state *as) 447{ 448 /* keep last values for debugging */ 449 as->last_ofdm_errors = as->ofdm_errors; 450 as->last_cck_errors = as->cck_errors; 451 as->last_listen = as->listen_time; 452 453 as->ofdm_errors = 0; 454 as->cck_errors = 0; 455 as->listen_time = 0; 456} 457 458 459/** 460 * ath5k_ani_calibration() - The main ANI calibration function 461 * 462 * We count OFDM and CCK errors relative to the time where we did not send or 463 * receive ("listen" time) and raise or lower immunity accordingly. 464 * This is called regularly (every second) from the calibration timer, but also 465 * when an error threshold has been reached. 466 * 467 * In order to synchronize access from different contexts, this should be 468 * called only indirectly by scheduling the ANI tasklet! 469 */ 470void 471ath5k_ani_calibration(struct ath5k_hw *ah) 472{ 473 struct ath5k_ani_state *as = &ah->ah_sc->ani_state; 474 int listen, ofdm_high, ofdm_low, cck_high, cck_low; 475 476 /* get listen time since last call and add it to the counter because we 477 * might not have restarted the "ani period" last time. 478 * always do this to calculate the busy time also in manual mode */ 479 listen = ath5k_hw_ani_get_listen_time(ah, as); 480 as->listen_time += listen; 481 482 if (as->ani_mode != ATH5K_ANI_MODE_AUTO) 483 return; 484 485 ath5k_ani_save_and_clear_phy_errors(ah, as); 486 487 ofdm_high = as->listen_time * ATH5K_ANI_OFDM_TRIG_HIGH / 1000; 488 cck_high = as->listen_time * ATH5K_ANI_CCK_TRIG_HIGH / 1000; 489 ofdm_low = as->listen_time * ATH5K_ANI_OFDM_TRIG_LOW / 1000; 490 cck_low = as->listen_time * ATH5K_ANI_CCK_TRIG_LOW / 1000; 491 492 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 493 "listen %d (now %d)", as->listen_time, listen); 494 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 495 "check high ofdm %d/%d cck %d/%d", 496 as->ofdm_errors, ofdm_high, as->cck_errors, cck_high); 497 498 if (as->ofdm_errors > ofdm_high || as->cck_errors > cck_high) { 499 /* too many PHY errors - we have to raise immunity */ 500 bool ofdm_flag = as->ofdm_errors > ofdm_high ? true : false; 501 ath5k_ani_raise_immunity(ah, as, ofdm_flag); 502 ath5k_ani_period_restart(ah, as); 503 504 } else if (as->listen_time > 5 * ATH5K_ANI_LISTEN_PERIOD) { 505 /* If more than 5 (TODO: why 5?) periods have passed and we got 506 * relatively little errors we can try to lower immunity */ 507 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 508 "check low ofdm %d/%d cck %d/%d", 509 as->ofdm_errors, ofdm_low, as->cck_errors, cck_low); 510 511 if (as->ofdm_errors <= ofdm_low && as->cck_errors <= cck_low) 512 ath5k_ani_lower_immunity(ah, as); 513 514 ath5k_ani_period_restart(ah, as); 515 } 516} 517 518 519/*** INTERRUPT HANDLER ***/ 520 521/** 522 * ath5k_ani_mib_intr() - Interrupt handler for ANI MIB counters 523 * 524 * Just read & reset the registers quickly, so they don't generate more 525 * interrupts, save the counters and schedule the tasklet to decide whether 526 * to raise immunity or not. 527 * 528 * We just need to handle PHY error counters, ath5k_hw_update_mib_counters() 529 * should take care of all "normal" MIB interrupts. 530 */ 531void 532ath5k_ani_mib_intr(struct ath5k_hw *ah) 533{ 534 struct ath5k_ani_state *as = &ah->ah_sc->ani_state; 535 536 /* nothing to do here if HW does not have PHY error counters - they 537 * can't be the reason for the MIB interrupt then */ 538 if (!ah->ah_capabilities.cap_has_phyerr_counters) 539 return; 540 541 /* not in use but clear anyways */ 542 ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT); 543 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT); 544 545 if (ah->ah_sc->ani_state.ani_mode != ATH5K_ANI_MODE_AUTO) 546 return; 547 548 /* if one of the errors triggered, we can get a superfluous second 549 * interrupt, even though we have already reset the register. the 550 * function detects that so we can return early */ 551 if (ath5k_ani_save_and_clear_phy_errors(ah, as) == 0) 552 return; 553 554 if (as->ofdm_errors > ATH5K_ANI_OFDM_TRIG_HIGH || 555 as->cck_errors > ATH5K_ANI_CCK_TRIG_HIGH) 556 tasklet_schedule(&ah->ah_sc->ani_tasklet); 557} 558 559 560/** 561 * ath5k_ani_phy_error_report() - Used by older HW to report PHY errors 562 * 563 * This is used by hardware without PHY error counters to report PHY errors 564 * on a frame-by-frame basis, instead of the interrupt. 565 */ 566void 567ath5k_ani_phy_error_report(struct ath5k_hw *ah, 568 enum ath5k_phy_error_code phyerr) 569{ 570 struct ath5k_ani_state *as = &ah->ah_sc->ani_state; 571 572 if (phyerr == AR5K_RX_PHY_ERROR_OFDM_TIMING) { 573 as->ofdm_errors++; 574 if (as->ofdm_errors > ATH5K_ANI_OFDM_TRIG_HIGH) 575 tasklet_schedule(&ah->ah_sc->ani_tasklet); 576 } else if (phyerr == AR5K_RX_PHY_ERROR_CCK_TIMING) { 577 as->cck_errors++; 578 if (as->cck_errors > ATH5K_ANI_CCK_TRIG_HIGH) 579 tasklet_schedule(&ah->ah_sc->ani_tasklet); 580 } 581} 582 583 584/*** INIT ***/ 585 586/** 587 * ath5k_enable_phy_err_counters() - Enable PHY error counters 588 * 589 * Enable PHY error counters for OFDM and CCK timing errors. 590 */ 591static void 592ath5k_enable_phy_err_counters(struct ath5k_hw *ah) 593{ 594 ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_OFDM_TRIG_HIGH, 595 AR5K_PHYERR_CNT1); 596 ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_CCK_TRIG_HIGH, 597 AR5K_PHYERR_CNT2); 598 ath5k_hw_reg_write(ah, AR5K_PHY_ERR_FIL_OFDM, AR5K_PHYERR_CNT1_MASK); 599 ath5k_hw_reg_write(ah, AR5K_PHY_ERR_FIL_CCK, AR5K_PHYERR_CNT2_MASK); 600 601 /* not in use */ 602 ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT); 603 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT); 604} 605 606 607/** 608 * ath5k_disable_phy_err_counters() - Disable PHY error counters 609 * 610 * Disable PHY error counters for OFDM and CCK timing errors. 611 */ 612static void 613ath5k_disable_phy_err_counters(struct ath5k_hw *ah) 614{ 615 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT1); 616 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT2); 617 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT1_MASK); 618 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT2_MASK); 619 620 /* not in use */ 621 ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT); 622 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT); 623} 624 625 626/** 627 * ath5k_ani_init() - Initialize ANI 628 * @mode: Which mode to use (auto, manual high, manual low, off) 629 * 630 * Initialize ANI according to mode. 631 */ 632void 633ath5k_ani_init(struct ath5k_hw *ah, enum ath5k_ani_mode mode) 634{ 635 /* ANI is only possible on 5212 and newer */ 636 if (ah->ah_version < AR5K_AR5212) 637 return; 638 639 /* clear old state information */ 640 memset(&ah->ah_sc->ani_state, 0, sizeof(ah->ah_sc->ani_state)); 641 642 /* older hardware has more spur levels than newer */ 643 if (ah->ah_mac_srev < AR5K_SREV_AR2414) 644 ah->ah_sc->ani_state.max_spur_level = 7; 645 else 646 ah->ah_sc->ani_state.max_spur_level = 2; 647 648 /* initial values for our ani parameters */ 649 if (mode == ATH5K_ANI_MODE_OFF) { 650 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "ANI off\n"); 651 } else if (mode == ATH5K_ANI_MODE_MANUAL_LOW) { 652 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 653 "ANI manual low -> high sensitivity\n"); 654 ath5k_ani_set_noise_immunity_level(ah, 0); 655 ath5k_ani_set_spur_immunity_level(ah, 0); 656 ath5k_ani_set_firstep_level(ah, 0); 657 ath5k_ani_set_ofdm_weak_signal_detection(ah, true); 658 ath5k_ani_set_cck_weak_signal_detection(ah, true); 659 } else if (mode == ATH5K_ANI_MODE_MANUAL_HIGH) { 660 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 661 "ANI manual high -> low sensitivity\n"); 662 ath5k_ani_set_noise_immunity_level(ah, 663 ATH5K_ANI_MAX_NOISE_IMM_LVL); 664 ath5k_ani_set_spur_immunity_level(ah, 665 ah->ah_sc->ani_state.max_spur_level); 666 ath5k_ani_set_firstep_level(ah, ATH5K_ANI_MAX_FIRSTEP_LVL); 667 ath5k_ani_set_ofdm_weak_signal_detection(ah, false); 668 ath5k_ani_set_cck_weak_signal_detection(ah, false); 669 } else if (mode == ATH5K_ANI_MODE_AUTO) { 670 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "ANI auto\n"); 671 ath5k_ani_set_noise_immunity_level(ah, 0); 672 ath5k_ani_set_spur_immunity_level(ah, 0); 673 ath5k_ani_set_firstep_level(ah, 0); 674 ath5k_ani_set_ofdm_weak_signal_detection(ah, true); 675 ath5k_ani_set_cck_weak_signal_detection(ah, false); 676 } 677 678 /* newer hardware has PHY error counter registers which we can use to 679 * get OFDM and CCK error counts. older hardware has to set rxfilter and 680 * report every single PHY error by calling ath5k_ani_phy_error_report() 681 */ 682 if (mode == ATH5K_ANI_MODE_AUTO) { 683 if (ah->ah_capabilities.cap_has_phyerr_counters) 684 ath5k_enable_phy_err_counters(ah); 685 else 686 ath5k_hw_set_rx_filter(ah, ath5k_hw_get_rx_filter(ah) | 687 AR5K_RX_FILTER_PHYERR); 688 } else { 689 if (ah->ah_capabilities.cap_has_phyerr_counters) 690 ath5k_disable_phy_err_counters(ah); 691 else 692 ath5k_hw_set_rx_filter(ah, ath5k_hw_get_rx_filter(ah) & 693 ~AR5K_RX_FILTER_PHYERR); 694 } 695 696 ah->ah_sc->ani_state.ani_mode = mode; 697} 698 699 700/*** DEBUG ***/ 701 702#ifdef CONFIG_ATH5K_DEBUG 703 704void 705ath5k_ani_print_counters(struct ath5k_hw *ah) 706{ 707 /* clears too */ 708 printk(KERN_NOTICE "ACK fail\t%d\n", 709 ath5k_hw_reg_read(ah, AR5K_ACK_FAIL)); 710 printk(KERN_NOTICE "RTS fail\t%d\n", 711 ath5k_hw_reg_read(ah, AR5K_RTS_FAIL)); 712 printk(KERN_NOTICE "RTS success\t%d\n", 713 ath5k_hw_reg_read(ah, AR5K_RTS_OK)); 714 printk(KERN_NOTICE "FCS error\t%d\n", 715 ath5k_hw_reg_read(ah, AR5K_FCS_FAIL)); 716 717 /* no clear */ 718 printk(KERN_NOTICE "tx\t%d\n", 719 ath5k_hw_reg_read(ah, AR5K_PROFCNT_TX)); 720 printk(KERN_NOTICE "rx\t%d\n", 721 ath5k_hw_reg_read(ah, AR5K_PROFCNT_RX)); 722 printk(KERN_NOTICE "busy\t%d\n", 723 ath5k_hw_reg_read(ah, AR5K_PROFCNT_RXCLR)); 724 printk(KERN_NOTICE "cycles\t%d\n", 725 ath5k_hw_reg_read(ah, AR5K_PROFCNT_CYCLE)); 726 727 printk(KERN_NOTICE "AR5K_PHYERR_CNT1\t%d\n", 728 ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT1)); 729 printk(KERN_NOTICE "AR5K_PHYERR_CNT2\t%d\n", 730 ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT2)); 731 printk(KERN_NOTICE "AR5K_OFDM_FIL_CNT\t%d\n", 732 ath5k_hw_reg_read(ah, AR5K_OFDM_FIL_CNT)); 733 printk(KERN_NOTICE "AR5K_CCK_FIL_CNT\t%d\n", 734 ath5k_hw_reg_read(ah, AR5K_CCK_FIL_CNT)); 735} 736 737#endif 738