Searched refs:WREG32_PLL_P (Results 1 - 4 of 4) sorted by relevance
| /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/gpu/drm/radeon/ |
| H A D | radeon_legacy_crtc.c | 229 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
252 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
793 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
797 WREG32_PLL_P(RADEON_P2PLL_CNTL,
805 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
809 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
813 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
822 WREG32_PLL_P(RADEON_P2PLL_CNTL,
841 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
868 WREG32_PLL_P(RADEON_VCLK_ECP_CNT
[all...] |
| H A D | radeon_legacy_tv.c | 749 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL);
751 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET);
755 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET);
760 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf);
761 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL);
763 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK);
764 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP);
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| H A D | radeon.h | 1193 #define WREG32_PLL_P(reg, val, mask) \ macro
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| H A D | radeon_legacy_encoders.c | 97 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
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Completed in 164 milliseconds