Searched refs:WREG32_P (Results 1 - 8 of 8) sorted by relevance
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/gpu/drm/radeon/ |
H A D | r600_audio.c | 164 WREG32_P(R600_AUDIO_ENABLE, enable ? 0x81000000 : 0x0, ~0x81000000); 236 WREG32_P(R600_AUDIO_TIMING, 0, ~0x301); 242 WREG32_P(R600_AUDIO_TIMING, 0x100, ~0x301);
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H A D | r600_hdmi.c | 293 WREG32_P(offset+R600_HDMI_CNTL, 0x00000001, ~0x00001001); 296 WREG32_P(offset+R600_HDMI_CNTL, 0x00001001, ~0x00001001); 340 WREG32_P(offset+R600_HDMI_CNTL, 0x00040000, ~0x001F0000); 402 WREG32_P(offset+R600_HDMI_IEC60958_2, iec, ~0x5000f); 495 WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0x1, ~0x1); 499 WREG32_P(AVIVO_TMDSA_CNTL, 0x4, ~0x4); 503 WREG32_P(AVIVO_LVTMA_CNTL, 0x4, ~0x4); 561 WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0, ~0x1); 565 WREG32_P(AVIVO_TMDSA_CNTL, 0, ~0x4); 569 WREG32_P(AVIVO_LVTMA_CNT [all...] |
H A D | radeon_cursor.c | 85 WREG32_P(RADEON_MM_DATA, 0, ~RADEON_CRTC_CUR_EN); 114 WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN |
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H A D | radeon_legacy_crtc.c | 311 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); 313 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | 315 WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask); 325 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); 327 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | 329 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask); 860 WREG32_P(RADEON_CLOCK_CNTL_INDEX, 881 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
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H A D | radeon_legacy_encoders.c | 346 WREG32_P(RADEON_DAC_CNTL, 1001 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); 1038 WREG32_P(RADEON_GPIOPAD_A, 0, ~1); 1088 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); 1214 WREG32_P(RADEON_GPIOPAD_A, 1, ~1); 1274 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
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H A D | radeon.h | 1186 #define WREG32_P(reg, val, mask) \ macro
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H A D | r600.c | 3214 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); 3218 WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); 3222 WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
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H A D | r100.c | 2260 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
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Completed in 172 milliseconds