Searched refs:VT1724_SPDIF_MASTER (Results 1 - 4 of 4) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/sound/pci/ice1712/
H A Denvy24ht.h143 #define VT1724_SPDIF_MASTER 0x10 /* S/PDIF input is master clock */ macro
H A Djuli.c545 outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
H A Dquartet.c893 outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
1030 outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
H A Dice1724.c122 return (inb(ICEMT1724(ice, RATE)) & VT1724_SPDIF_MASTER) ? 1 : 0;
1817 outb(oval | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));

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