Searched refs:VR_CTL (Results 1 - 16 of 16) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-common/
H A Dclocks-init.c70 bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE);
H A Ddpmc_modes.S65 P0.H = hi(VR_CTL);
66 P0.L = lo(VR_CTL);
109 P0.H = hi(VR_CTL);
110 P0.L = lo(VR_CTL);
146 P0.H = hi(VR_CTL);
147 P0.L = lo(VR_CTL);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h27 #define bfin_read_VR_CTL() bfin_read16(VR_CTL)
722 /* Writing to VR_CTL initiates a PLL relock sequence. */
736 bfin_write16(VR_CTL, val);
H A DdefBF532.h22 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF51x_base.h23 #define bfin_read_VR_CTL() bfin_read16(VR_CTL)
1086 /* Writing to VR_CTL initiates a PLL relock sequence. */
1102 bfin_write16(VR_CTL, val);
H A DdefBF51x_base.h18 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF52x_base.h23 #define bfin_read_VR_CTL() bfin_read16(VR_CTL)
1138 /* Writing to VR_CTL initiates a PLL relock sequence. */
1154 bfin_write16(VR_CTL, val);
H A DdefBF52x_base.h20 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h19 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ macro
H A DcdefBF534.h22 #define bfin_read_VR_CTL() bfin_read16(VR_CTL)
1775 /* Writing to VR_CTL initiates a PLL relock sequence. */
1789 bfin_write16(VR_CTL, val);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf561/include/mach/
H A DdefBF561.h25 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ macro
H A DcdefBF561.h26 #define bfin_read_VR_CTL() bfin_read16(VR_CTL)
1562 /* Writing to VR_CTL initiates a PLL relock sequence. */
1578 bfin_write16(VR_CTL, val);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h23 #define bfin_read_VR_CTL() bfin_read16(VR_CTL)
2055 /* Writing to VR_CTL initiates a PLL relock sequence. */
2071 bfin_write16(VR_CTL, val);
H A DdefBF539.h22 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h19 #define VR_CTL 0xffc00008 /* Voltage Regulator Control Register */ macro
H A DcdefBF54x_base.h23 #define bfin_read_VR_CTL() bfin_read16(VR_CTL)
2679 /* Writing to VR_CTL initiates a PLL relock sequence. */
2697 bfin_write16(VR_CTL, val);

Completed in 336 milliseconds