Searched refs:UDCCR (Results 1 - 7 of 7) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/usb/gadget/
H A Dpxa27x_udc.c80 tmp = udc_readl(udc, UDCCR);
171 tmp = i? udc_ep_readl(ep, UDCCR) : udc_readl(udc, UDCCR);
325 * - we rely on UDCCR register "active interface" and "active altsetting".
413 * udc_set_mask_UDCCR - set bits in UDCCR
415 * @mask: bits to set in UDCCR
417 * Sets bits in UDCCR, leaving DME and FST bits as they were.
421 u32 udccr = udc_readl(udc, UDCCR);
422 udc_writel(udc, UDCCR,
427 * udc_clear_mask_UDCCR - clears bits in UDCCR
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H A Dpxa25x_udc.h181 u32 udccr = UDCCR;
H A Dpxa25x_udc.c205 /* The UDCCR reg contains mask and interrupt status bits,
212 UDCCR = (UDCCR & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS);
217 UDCCR = (UDCCR & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS);
223 __u32 udccr = UDCCR & UDCCR_MASK_BITS;
225 UDCCR = udccr | (mask & ~UDCCR_MASK_BITS);
1057 tmp = UDCCR;
1239 if (!(UDCCR & UDCCR_UDA))
1752 u32 udccr = UDCCR;
[all...]
H A Dpxa27x_udc.h35 #define UDCCR 0x0000 /* UDC Control Register */ macro
182 * UDCCR = UDC Endpoint Configuration Registers
336 * @udccr_value: save register of UDCCR for suspend/resume
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-pxa/include/mach/
H A Dpxa25x-udc.h12 #define UDCCR __REG(0x40600000) /* UDC Control Register */ macro
H A Dpxa27x-udc.h8 #define UDCCR __REG(0x40600000) /* UDC Control Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-ixp4xx/include/mach/
H A Dixp4xx-regs.h423 #define UDCCR IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0000) macro

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