Searched refs:SIC_ISR0 (Results 1 - 9 of 9) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-common/
H A Dints-priority.c1300 #if defined(SIC_ISR0) || defined(SICA_ISR0)
1380 #if defined(SIC_ISR0) || defined(SICA_ISR0)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF51x_base.h54 #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
55 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
56 #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
57 #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
H A DdefBF51x_base.h33 #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF52x_base.h54 #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
55 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
56 #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
57 #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
H A DdefBF52x_base.h36 #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h42 #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
43 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
46 #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0))
47 #define bfin_write_SIC_ISR(x, val) bfin_write32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0), val)
H A DdefBF539.h40 #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/
H A DcdefBF54x_base.h52 #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
53 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
58 #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2))
59 #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val)
H A DdefBF54x_base.h41 #define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */ macro
1514 /* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */

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