Searched refs:SIC_IMASK0 (Results 1 - 9 of 9) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-common/
H A Ddpmc_modes.S283 #ifdef SIC_IMASK0
284 PM_SYS_PUSH(SIC_IMASK0)
820 #ifdef SIC_IMASK0
821 PM_SYS_POP(SIC_IMASK0)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF51x_base.h40 #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
41 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
42 #define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
43 #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
H A DdefBF51x_base.h28 #define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF52x_base.h40 #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
41 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
42 #define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
43 #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
H A DdefBF52x_base.h31 #define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h36 #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
37 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
40 #define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0))
41 #define bfin_write_SIC_IMASK(x, val) bfin_write32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0), val)
H A DdefBF539.h35 #define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/
H A DcdefBF54x_base.h43 #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
44 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
49 #define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2))
50 #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val)
H A DdefBF54x_base.h38 #define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */ macro
1514 /* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */

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