Searched refs:RF90_PATH_D (Results 1 - 10 of 10) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/staging/rtl8192su/
H A Dr8192S_rtl8225.c155 //u32 OrgStoreRFIntSW[RF90_PATH_D+1];
230 case RF90_PATH_D:
259 case RF90_PATH_D:
271 case RF90_PATH_D:
H A Dr8192S_phy.h80 RF90_PATH_D = 3, //Radio Path D enumerator in enum:_RF90_RADIO_PATH
H A Dr8192S_phy.c1054 case RF90_PATH_D:
1317 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
1323 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
1329 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
1335 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
1341 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
1347 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
1353 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1359 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1
1365 priv->PHYRegDef[RF90_PATH_D]
[all...]
H A Dr8192S_rtl6052.c421 //u32 OrgStoreRFIntSW[RF90_PATH_D+1];
499 case RF90_PATH_D:
526 case RF90_PATH_D:
538 case RF90_PATH_D:
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/staging/rtl8192u/
H A Dr819xU_phy.c73 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
587 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
593 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
599 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
605 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
611 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
617 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
623 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
629 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1
635 priv->PHYRegDef[RF90_PATH_D]
[all...]
H A Dr8190_rtl8256.c143 case RF90_PATH_D:
200 case RF90_PATH_D:
219 case RF90_PATH_D:
H A Dr819xU_phy.h48 RF90_PATH_D = 3, //Radio Path D enumerator in enum:_RF90_RADIO_PATH
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/staging/rtl8192e/
H A Dr819xE_phy.h91 RF90_PATH_D = 3, enumerator in enum:_RF90_RADIO_PATH
H A Dr819xE_phy.c1439 else if(eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
1450 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
2061 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
2067 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
2073 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
2079 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
2085 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
2091 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
2097 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2103 priv->PHYRegDef[RF90_PATH_D]
[all...]
H A Dr8190_rtl8256.c137 case RF90_PATH_D:
195 case RF90_PATH_D:
214 case RF90_PATH_D:

Completed in 129 milliseconds