1/****************************************************************************** 2 * 3 * (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved. 4 * 5 * Module: HalRf6052.c ( Source C File) 6 * 7 * Note: Provide RF 6052 series relative API. 8 * 9 * Function: 10 * 11 * Export: 12 * 13 * Abbrev: 14 * 15 * History: 16 * Data Who Remark 17 * 18 * 09/25/2008 MHC Create initial version. 19 * 11/05/2008 MHC Add API for tw power setting. 20 * 21 * 22******************************************************************************/ 23#include "r8192U.h" 24#include "r8192S_rtl6052.h" 25 26#include "r8192S_hw.h" 27#include "r8192S_phyreg.h" 28#include "r8192S_phy.h" 29 30 31/*---------------------------Define Local Constant---------------------------*/ 32// Define local structure for debug!!!!! 33typedef struct RF_Shadow_Compare_Map { 34 // Shadow register value 35 u32 Value; 36 // Compare or not flag 37 u8 Compare; 38 // Record If it had ever modified unpredicted 39 u8 ErrorOrNot; 40 // Recorver Flag 41 u8 Recorver; 42 // 43 u8 Driver_Write; 44}RF_SHADOW_T; 45/*---------------------------Define Local Constant---------------------------*/ 46 47 48/*------------------------Define global variable-----------------------------*/ 49/*------------------------Define global variable-----------------------------*/ 50 51 52 53 54/*---------------------Define local function prototype-----------------------*/ 55void phy_RF6052_Config_HardCode(struct net_device* dev); 56 57RT_STATUS phy_RF6052_Config_ParaFile(struct net_device* dev); 58/*---------------------Define local function prototype-----------------------*/ 59 60/*------------------------Define function prototype--------------------------*/ 61extern void RF_ChangeTxPath(struct net_device* dev, u16 DataRate); 62 63/*------------------------Define function prototype--------------------------*/ 64 65/*------------------------Define local variable------------------------------*/ 66// 2008/11/20 MH For Debug only, RF 67static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];// = {{0}};//FIXLZM 68/*------------------------Define local variable------------------------------*/ 69 70/*------------------------Define function prototype--------------------------*/ 71/*----------------------------------------------------------------------------- 72 * Function: RF_ChangeTxPath 73 * 74 * Overview: For RL6052, we must change some RF settign for 1T or 2T. 75 * 76 * Input: u16 DataRate // 0x80-8f, 0x90-9f 77 * 78 * Output: NONE 79 * 80 * Return: NONE 81 * 82 * Revised History: 83 * When Who Remark 84 * 09/25/2008 MHC Create Version 0. 85 * Firmwaer support the utility later. 86 * 87 *---------------------------------------------------------------------------*/ 88extern void RF_ChangeTxPath(struct net_device* dev, u16 DataRate) 89{ 90} /* RF_ChangeTxPath */ 91 92 93/*----------------------------------------------------------------------------- 94 * Function: PHY_RF6052SetBandwidth() 95 * 96 * Overview: This function is called by SetBWModeCallback8190Pci() only 97 * 98 * Input: PADAPTER Adapter 99 * WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M 100 * 101 * Output: NONE 102 * 103 * Return: NONE 104 * 105 * Note: For RF type 0222D 106 *---------------------------------------------------------------------------*/ 107void PHY_RF6052SetBandwidth(struct net_device* dev, HT_CHANNEL_WIDTH Bandwidth) //20M or 40M 108{ 109 //u8 eRFPath; 110 //struct r8192_priv *priv = ieee80211_priv(dev); 111 112 113 //if (priv->card_8192 == NIC_8192SE) 114 { 115 switch(Bandwidth) 116 { 117 case HT_CHANNEL_WIDTH_20: 118 //if (priv->card_8192_version >= VERSION_8192S_BCUT) 119 // rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58); 120 121 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x01); 122 break; 123 case HT_CHANNEL_WIDTH_20_40: 124 //if (priv->card_8192_version >= VERSION_8192S_BCUT) 125 // rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18); 126 127 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x00); 128 break; 129 default: 130 RT_TRACE(COMP_DBG, "PHY_SetRF6052Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth); 131 break; 132 } 133 } 134// else 135} 136 137 138/*----------------------------------------------------------------------------- 139 * Function: PHY_RF6052SetCckTxPower 140 * 141 * Overview: 142 * 143 * Input: NONE 144 * 145 * Output: NONE 146 * 147 * Return: NONE 148 * 149 * Revised History: 150 * When Who Remark 151 * 11/05/2008 MHC Simulate 8192series.. 152 * 153 *---------------------------------------------------------------------------*/ 154extern void PHY_RF6052SetCckTxPower(struct net_device* dev, u8 powerlevel) 155{ 156 struct r8192_priv *priv = ieee80211_priv(dev); 157 u32 TxAGC=0; 158 159 if(priv->ieee80211->scanning == 1) 160 TxAGC = 0x3f; 161 else if(priv->bDynamicTxLowPower == true)//cosa 04282008 for cck long range 162 TxAGC = 0x22; 163 else 164 TxAGC = powerlevel; 165 166 //cosa add for lenovo, to pass the safety spec, don't increase power index for different rates. 167 if(priv->bIgnoreDiffRateTxPowerOffset) 168 TxAGC = powerlevel; 169 170 if(TxAGC > RF6052_MAX_TX_PWR) 171 TxAGC = RF6052_MAX_TX_PWR; 172 173 //printk("CCK PWR= %x\n", TxAGC); 174 rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); 175 176} /* PHY_RF6052SetCckTxPower */ 177 178 179 180/*----------------------------------------------------------------------------- 181 * Function: PHY_RF6052SetOFDMTxPower 182 * 183 * Overview: For legacy and HY OFDM, we must read EEPROM TX power index for 184 * different channel and read original value in TX power register area from 185 * 0xe00. We increase offset and original value to be correct tx pwr. 186 * 187 * Input: NONE 188 * 189 * Output: NONE 190 * 191 * Return: NONE 192 * 193 * Revised History: 194 * When Who Remark 195 * 11/05/2008 MHC Simulate 8192 series method. 196* 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to 197 * A/B pwr difference or legacy/HT pwr diff. 198 * 2. We concern with path B legacy/HT OFDM difference. 199 * 01/22/2009 MHC Support new EPRO format from SD3. 200 *---------------------------------------------------------------------------*/ 201extern void PHY_RF6052SetOFDMTxPower(struct net_device* dev, u8 powerlevel) 202{ 203 struct r8192_priv *priv = ieee80211_priv(dev); 204 u32 writeVal, powerBase0, powerBase1; 205 u8 index = 0; 206 u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; 207 //u8 byte0, byte1, byte2, byte3; 208 u8 Channel = priv->ieee80211->current_network.channel; 209 u8 rfa_pwr[4]; 210 u8 rfa_lower_bound = 0, rfa_upper_bound = 0 /*, rfa_htpwr, rfa_legacypwr*/; 211 u8 i; 212 u8 rf_pwr_diff = 0; 213 u8 Legacy_pwrdiff=0, HT20_pwrdiff=0, BandEdge_Pwrdiff=0; 214 u8 ofdm_bandedge_chnl_low=0, ofdm_bandedge_chnl_high=0; 215 216 217 // We only care about the path A for legacy. 218 if (priv->EEPROMVersion != 2) 219 powerBase0 = powerlevel + (priv->LegacyHTTxPowerDiff & 0xf); 220 else if (priv->EEPROMVersion == 2) // Defined by SD1 Jong 221 { 222 // 223 // 2009/01/21 MH Support new EEPROM format from SD3 requirement 224 // 225 Legacy_pwrdiff = priv->TxPwrLegacyHtDiff[RF90_PATH_A][Channel-1]; 226 // For legacy OFDM, tx pwr always > HT OFDM pwr. We do not care Path B 227 // legacy OFDM pwr diff. NO BB register to notify HW. 228 powerBase0 = powerlevel + Legacy_pwrdiff; 229 //RTPRINT(FPHY, PHY_TXPWR, (" [LagacyToHT40 pwr diff = %d]\n", Legacy_pwrdiff)); 230 231 // Band Edge scheme is enabled for FCC mode 232 if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/) 233 { 234 ofdm_bandedge_chnl_low = 1; 235 ofdm_bandedge_chnl_high = 11; 236 BandEdge_Pwrdiff = 0; 237 if (Channel <= ofdm_bandedge_chnl_low) 238 BandEdge_Pwrdiff = priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0]; 239 else if (Channel >= ofdm_bandedge_chnl_high) 240 { 241 BandEdge_Pwrdiff = priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][1]; 242 } 243 powerBase0 -= BandEdge_Pwrdiff; 244 if (Channel <= ofdm_bandedge_chnl_low || Channel >= ofdm_bandedge_chnl_high) 245 { 246 //RTPRINT(FPHY, PHY_TXPWR, (" [OFDM band-edge channel = %d, pwr diff = %d]\n", 247 //Channel, BandEdge_Pwrdiff)); 248 } 249 } 250 //RTPRINT(FPHY, PHY_TXPWR, (" [OFDM power base index = 0x%x]\n", powerBase0)); 251 } 252 powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; 253 254 //MCS rates 255 if(priv->EEPROMVersion == 2) 256 { 257 //Cosa add for new EEPROM content. 02102009 258 259 //Check HT20 to HT40 diff 260 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) 261 { 262 // HT 20<->40 pwr diff 263 HT20_pwrdiff = priv->TxPwrHt20Diff[RF90_PATH_A][Channel-1]; 264 265 // Calculate Antenna pwr diff 266 if (HT20_pwrdiff < 8) // 0~+7 267 powerlevel += HT20_pwrdiff; 268 else // index8-15=-8~-1 269 powerlevel -= (16-HT20_pwrdiff); 270 271 //RTPRINT(FPHY, PHY_TXPWR, (" [HT20 to HT40 pwrdiff = %d]\n", HT20_pwrdiff)); 272 //RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index = 0x%x]\n", powerlevel)); 273 } 274 275 // Band Edge scheme is enabled for FCC mode 276 if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/) 277 { 278 BandEdge_Pwrdiff = 0; 279 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) 280 { 281 if (Channel <= 3) 282 BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt40[RF90_PATH_A][0]; 283 else if (Channel >= 9) 284 BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt40[RF90_PATH_A][1]; 285 if (Channel <= 3 || Channel >= 9) 286 { 287 //RTPRINT(FPHY, PHY_TXPWR, (" [HT40 band-edge channel = %d, pwr diff = %d]\n", 288 //Channel, BandEdge_Pwrdiff)); 289 } 290 } 291 else if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) 292 { 293 if (Channel <= 1) 294 BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt20[RF90_PATH_A][0]; 295 else if (Channel >= 11) 296 BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt20[RF90_PATH_A][1]; 297 if (Channel <= 1 || Channel >= 11) 298 { 299 //RTPRINT(FPHY, PHY_TXPWR, (" [HT20 band-edge channel = %d, pwr diff = %d]\n", 300 //Channel, BandEdge_Pwrdiff)); 301 } 302 } 303 powerlevel -= BandEdge_Pwrdiff; 304 //RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index = 0x%x]\n", powerlevel)); 305 } 306 } 307 powerBase1 = powerlevel; 308 powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; 309 310 //RTPRINT(FPHY, PHY_TXPWR, (" [Legacy/HT power index= %x/%x]\n", powerBase0, powerBase1)); 311 312 for(index=0; index<6; index++) 313 { 314 // 315 // Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate 316 // 317 //cosa add for lenovo, to pass the safety spec, don't increase power index for different rates. 318 if(priv->bIgnoreDiffRateTxPowerOffset) 319 writeVal = ((index<2)?powerBase0:powerBase1); 320 else 321 writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1); 322 323 //RTPRINT(FPHY, PHY_TXPWR, ("Reg 0x%x, Original=%x writeVal=%x\n", 324 //RegOffset[index], priv->MCSTxPowerLevelOriginalOffset[index], writeVal)); 325 326 // 327 // If path A and Path B coexist, we must limit Path A tx power. 328 // Protect Path B pwr over or underflow. We need to calculate upper and 329 // lower bound of path A tx power. 330 // 331 if (priv->rf_type == RF_2T2R) 332 { 333 rf_pwr_diff = priv->AntennaTxPwDiff[0]; 334 //RTPRINT(FPHY, PHY_TXPWR, ("2T2R RF-B to RF-A PWR DIFF=%d\n", rf_pwr_diff)); 335 336 if (rf_pwr_diff >= 8) // Diff=-8~-1 337 { // Prevent underflow!! 338 rfa_lower_bound = 0x10-rf_pwr_diff; 339 //RTPRINT(FPHY, PHY_TXPWR, ("rfa_lower_bound= %d\n", rfa_lower_bound)); 340 } 341 else if (rf_pwr_diff >= 0) // Diff = 0-7 342 { 343 rfa_upper_bound = RF6052_MAX_TX_PWR-rf_pwr_diff; 344 //RTPRINT(FPHY, PHY_TXPWR, ("rfa_upper_bound= %d\n", rfa_upper_bound)); 345 } 346 } 347 348 for (i= 0; i <4; i++) 349 { 350 rfa_pwr[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8)); 351 if (rfa_pwr[i] > RF6052_MAX_TX_PWR) 352 rfa_pwr[i] = RF6052_MAX_TX_PWR; 353 354 // 355 // If path A and Path B coexist, we must limit Path A tx power. 356 // Protect Path B pwr under/over flow. We need to calculate upper and 357 // lower bound of path A tx power. 358 // 359 if (priv->rf_type == RF_2T2R) 360 { 361 if (rf_pwr_diff >= 8) // Diff=-8~-1 362 { // Prevent underflow!! 363 if (rfa_pwr[i] <rfa_lower_bound) 364 { 365 //RTPRINT(FPHY, PHY_TXPWR, ("Underflow")); 366 rfa_pwr[i] = rfa_lower_bound; 367 } 368 } 369 else if (rf_pwr_diff >= 1) // Diff = 0-7 370 { // Prevent overflow 371 if (rfa_pwr[i] > rfa_upper_bound) 372 { 373 //RTPRINT(FPHY, PHY_TXPWR, ("Overflow")); 374 rfa_pwr[i] = rfa_upper_bound; 375 } 376 } 377 //RTPRINT(FPHY, PHY_TXPWR, ("rfa_pwr[%d]=%x\n", i, rfa_pwr[i])); 378 } 379 380 } 381 382 // 383 // Add description: PWDB > threshold!!!High power issue!! 384 // We must decrease tx power !! Why is the value ??? 385 // 386 if(priv->bDynamicTxHighPower == TRUE) 387 { 388 // For MCS rate 389 if(index > 1) 390 { 391 writeVal = 0x03030303; 392 } 393 // For Legacy rate 394 else 395 { 396 writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0]; 397 } 398 //RTPRINT(FPHY, PHY_TXPWR, ("HighPower=%08x\n", writeVal)); 399 } 400 else 401 { 402 writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0]; 403 //RTPRINT(FPHY, PHY_TXPWR, ("NormalPower=%08x\n", writeVal)); 404 } 405 406 // 407 // Write different rate set tx power index. 408 // 409 //if (DCMD_Test_Flag == 0) 410 rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); 411 } 412 413} /* PHY_RF6052SetOFDMTxPower */ 414 415RT_STATUS PHY_RF6052_Config(struct net_device* dev) 416{ 417 struct r8192_priv *priv = ieee80211_priv(dev); 418 RT_STATUS rtStatus = RT_STATUS_SUCCESS; 419 //RF90_RADIO_PATH_E eRFPath; 420 //BB_REGISTER_DEFINITION_T *pPhyReg; 421 //u32 OrgStoreRFIntSW[RF90_PATH_D+1]; 422 423 // 424 // Initialize general global value 425 // 426 // TODO: Extend RF_PATH_C and RF_PATH_D in the future 427 if(priv->rf_type == RF_1T1R) 428 priv->NumTotalRFPath = 1; 429 else 430 priv->NumTotalRFPath = 2; 431 432 // 433 // Config BB and RF 434 // 435// switch( priv->bRegHwParaFile ) 436// { 437// case 0: 438// phy_RF6052_Config_HardCode(dev); 439// break; 440 441// case 1: 442 rtStatus = phy_RF6052_Config_ParaFile(dev); 443// break; 444 445// case 2: 446 // Partial Modify. 447// phy_RF6052_Config_HardCode(dev); 448// phy_RF6052_Config_ParaFile(dev); 449// break; 450 451// default: 452// phy_RF6052_Config_HardCode(dev); 453// break; 454// } 455 return rtStatus; 456 457} 458 459void phy_RF6052_Config_HardCode(struct net_device* dev) 460{ 461 462 // Set Default Bandwidth to 20M 463 //Adapter->HalFunc .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20); 464 465 // TODO: Set Default Channel to channel one for RTL8225 466 467} 468 469RT_STATUS phy_RF6052_Config_ParaFile(struct net_device* dev) 470{ 471 u32 u4RegValue = 0; 472 //static s1Byte szRadioAFile[] = RTL819X_PHY_RADIO_A; 473 //static s1Byte szRadioBFile[] = RTL819X_PHY_RADIO_B; 474 //static s1Byte szRadioBGMFile[] = RTL819X_PHY_RADIO_B_GM; 475 u8 eRFPath; 476 RT_STATUS rtStatus = RT_STATUS_SUCCESS; 477 struct r8192_priv *priv = ieee80211_priv(dev); 478 BB_REGISTER_DEFINITION_T *pPhyReg; 479 //u8 eCheckItem; 480 481 482 //3//----------------------------------------------------------------- 483 //3// <2> Initialize RF 484 //3//----------------------------------------------------------------- 485 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) 486 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) 487 { 488 489 pPhyReg = &priv->PHYRegDef[eRFPath]; 490 491 /*----Store original RFENV control type----*/ 492 switch(eRFPath) 493 { 494 case RF90_PATH_A: 495 case RF90_PATH_C: 496 u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV); 497 break; 498 case RF90_PATH_B : 499 case RF90_PATH_D: 500 u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16); 501 break; 502 } 503 504 /*----Set RF_ENV enable----*/ 505 rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); 506 507 /*----Set RF_ENV output high----*/ 508 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); 509 510 /* Set bit number of Address and Data for RF register */ 511 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255 512 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255 513 514 515 /*----Initialize RF fom connfiguration file----*/ 516 switch(eRFPath) 517 { 518 case RF90_PATH_A: 519 rtStatus= rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); 520 break; 521 case RF90_PATH_B: 522 rtStatus= rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); 523 break; 524 case RF90_PATH_C: 525 break; 526 case RF90_PATH_D: 527 break; 528 } 529 530 /*----Restore RFENV control type----*/; 531 switch(eRFPath) 532 { 533 case RF90_PATH_A: 534 case RF90_PATH_C: 535 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); 536 break; 537 case RF90_PATH_B : 538 case RF90_PATH_D: 539 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); 540 break; 541 } 542 543 if(rtStatus != RT_STATUS_SUCCESS){ 544 printk("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath); 545 goto phy_RF6052_Config_ParaFile_Fail; 546 } 547 548 } 549 550 RT_TRACE(COMP_INIT, "<---phy_RF6052_Config_ParaFile()\n"); 551 return rtStatus; 552 553phy_RF6052_Config_ParaFile_Fail: 554 return rtStatus; 555} 556 557 558// 559// ==> RF shadow Operation API Code Section!!! 560// 561/*----------------------------------------------------------------------------- 562 * Function: PHY_RFShadowRead 563 * PHY_RFShadowWrite 564 * PHY_RFShadowCompare 565 * PHY_RFShadowRecorver 566 * PHY_RFShadowCompareAll 567 * PHY_RFShadowRecorverAll 568 * PHY_RFShadowCompareFlagSet 569 * PHY_RFShadowRecorverFlagSet 570 * 571 * Overview: When we set RF register, we must write shadow at first. 572 * When we are running, we must compare shadow abd locate error addr. 573 * Decide to recorver or not. 574 * 575 * Input: NONE 576 * 577 * Output: NONE 578 * 579 * Return: NONE 580 * 581 * Revised History: 582 * When Who Remark 583 * 11/20/2008 MHC Create Version 0. 584 * 585 *---------------------------------------------------------------------------*/ 586extern u32 PHY_RFShadowRead( 587 struct net_device * dev, 588 RF90_RADIO_PATH_E eRFPath, 589 u32 Offset) 590{ 591 return RF_Shadow[eRFPath][Offset].Value; 592 593} /* PHY_RFShadowRead */ 594 595 596extern void PHY_RFShadowWrite( 597 struct net_device * dev, 598 u32 eRFPath, 599 u32 Offset, 600 u32 Data) 601{ 602 //RF_Shadow[eRFPath][Offset].Value = (Data & bMask20Bits); 603 RF_Shadow[eRFPath][Offset].Value = (Data & bRFRegOffsetMask); 604 RF_Shadow[eRFPath][Offset].Driver_Write = true; 605 606} /* PHY_RFShadowWrite */ 607 608 609extern void PHY_RFShadowCompare( 610 struct net_device * dev, 611 RF90_RADIO_PATH_E eRFPath, 612 u32 Offset) 613{ 614 u32 reg; 615 616 // Check if we need to check the register 617 if (RF_Shadow[eRFPath][Offset].Compare == true) 618 { 619 reg = rtl8192_phy_QueryRFReg(dev, eRFPath, Offset, bRFRegOffsetMask); 620 // Compare shadow and real rf register for 20bits!! 621 if (RF_Shadow[eRFPath][Offset].Value != reg) 622 { 623 // Locate error position. 624 RF_Shadow[eRFPath][Offset].ErrorOrNot = true; 625 RT_TRACE(COMP_INIT, "PHY_RFShadowCompare RF-%d Addr%02xErr = %05x", eRFPath, Offset, reg); 626 } 627 } 628 629} /* PHY_RFShadowCompare */ 630 631extern void PHY_RFShadowRecorver( 632 struct net_device * dev, 633 RF90_RADIO_PATH_E eRFPath, 634 u32 Offset) 635{ 636 // Check if the address is error 637 if (RF_Shadow[eRFPath][Offset].ErrorOrNot == true) 638 { 639 // Check if we need to recorver the register. 640 if (RF_Shadow[eRFPath][Offset].Recorver == true) 641 { 642 rtl8192_phy_SetRFReg(dev, eRFPath, Offset, bRFRegOffsetMask, RF_Shadow[eRFPath][Offset].Value); 643 RT_TRACE(COMP_INIT, "PHY_RFShadowRecorver RF-%d Addr%02x=%05x", 644 eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value); 645 } 646 } 647 648} /* PHY_RFShadowRecorver */ 649 650 651extern void PHY_RFShadowCompareAll(struct net_device * dev) 652{ 653 u32 eRFPath; 654 u32 Offset; 655 656 for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) 657 { 658 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) 659 { 660 PHY_RFShadowCompare(dev, (RF90_RADIO_PATH_E)eRFPath, Offset); 661 } 662 } 663 664} /* PHY_RFShadowCompareAll */ 665 666 667extern void PHY_RFShadowRecorverAll(struct net_device * dev) 668{ 669 u32 eRFPath; 670 u32 Offset; 671 672 for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) 673 { 674 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) 675 { 676 PHY_RFShadowRecorver(dev, (RF90_RADIO_PATH_E)eRFPath, Offset); 677 } 678 } 679 680} /* PHY_RFShadowRecorverAll */ 681 682 683extern void PHY_RFShadowCompareFlagSet( 684 struct net_device * dev, 685 RF90_RADIO_PATH_E eRFPath, 686 u32 Offset, 687 u8 Type) 688{ 689 // Set True or False!!! 690 RF_Shadow[eRFPath][Offset].Compare = Type; 691 692} /* PHY_RFShadowCompareFlagSet */ 693 694 695extern void PHY_RFShadowRecorverFlagSet( 696 struct net_device * dev, 697 RF90_RADIO_PATH_E eRFPath, 698 u32 Offset, 699 u8 Type) 700{ 701 // Set True or False!!! 702 RF_Shadow[eRFPath][Offset].Recorver= Type; 703 704} /* PHY_RFShadowRecorverFlagSet */ 705 706 707extern void PHY_RFShadowCompareFlagSetAll(struct net_device * dev) 708{ 709 u32 eRFPath; 710 u32 Offset; 711 712 for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) 713 { 714 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) 715 { 716 // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! 717 if (Offset != 0x26 && Offset != 0x27) 718 PHY_RFShadowCompareFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, FALSE); 719 else 720 PHY_RFShadowCompareFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, TRUE); 721 } 722 } 723 724} /* PHY_RFShadowCompareFlagSetAll */ 725 726 727extern void PHY_RFShadowRecorverFlagSetAll(struct net_device * dev) 728{ 729 u32 eRFPath; 730 u32 Offset; 731 732 for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) 733 { 734 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) 735 { 736 // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! 737 if (Offset != 0x26 && Offset != 0x27) 738 PHY_RFShadowRecorverFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, FALSE); 739 else 740 PHY_RFShadowRecorverFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, TRUE); 741 } 742 } 743 744} /* PHY_RFShadowCompareFlagSetAll */ 745 746 747 748extern void PHY_RFShadowRefresh(struct net_device * dev) 749{ 750 u32 eRFPath; 751 u32 Offset; 752 753 for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) 754 { 755 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) 756 { 757 RF_Shadow[eRFPath][Offset].Value = 0; 758 RF_Shadow[eRFPath][Offset].Compare = false; 759 RF_Shadow[eRFPath][Offset].Recorver = false; 760 RF_Shadow[eRFPath][Offset].ErrorOrNot = false; 761 RF_Shadow[eRFPath][Offset].Driver_Write = false; 762 } 763 } 764 765} /* PHY_RFShadowRead */ 766 767/* End of HalRf6052.c */ 768