Searched refs:REG_RMW_FIELD (Results 1 - 14 of 14) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/net/wireless/ath/ath9k/
H A Dar9003_phy.c98 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
156 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
158 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
160 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
163 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
166 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
174 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
176 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
178 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
185 REG_RMW_FIELD(a
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H A Dar9003_paprd.c22 REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B0,
24 REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B1,
26 REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B2,
56 REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2AM, AR_PHY_PAPRD_AM2AM_MASK, am_mask);
57 REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK, am_mask);
58 REG_RMW_FIELD(ah, AR_PHY_PAPRD_HT40, AR_PHY_PAPRD_HT40_MASK, ht40_mask);
61 REG_RMW_FIELD(ah, ctrl0[i],
63 REG_RMW_FIELD(ah, ctrl1[i],
65 REG_RMW_FIELD(ah, ctrl1[i],
67 REG_RMW_FIELD(a
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H A Dar9002_calib.c28 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
249 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
252 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
404 REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
406 REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
434 REG_RMW_FIELD(ah,
467 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
469 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
471 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
473 REG_RMW_FIELD(a
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H A Dbtcoex.c113 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
133 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
137 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
180 REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
181 REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
H A Dar5008_phy.c935 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
937 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
945 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
947 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1070 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1073 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1076 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1079 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1099 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1102 REG_RMW_FIELD(a
[all...]
H A Dar9003_calib.c33 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
45 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
47 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
271 REG_RMW_FIELD(ah, offset_array[i],
274 REG_RMW_FIELD(ah, offset_array[i],
653 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
656 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
683 REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
689 REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
712 REG_RMW_FIELD(a
[all...]
H A Deeprom_4k.c430 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
432 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
434 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
436 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
875 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
877 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
879 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
882 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
886 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
889 REG_RMW_FIELD(a
[all...]
H A Deeprom_def.c63 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
65 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
68 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
321 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
324 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
327 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
330 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
348 REG_RMW_FIELD(ah,
351 REG_RMW_FIELD(ah,
455 REG_RMW_FIELD(a
[all...]
H A Deeprom_9287.c503 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
505 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
507 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
509 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
1046 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1049 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1052 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1055 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1062 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1065 REG_RMW_FIELD(a
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H A Dar9003_eeprom.c998 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
999 REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB, bias >> 2);
1000 REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1);
1047 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
1050 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
1053 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value);
1056 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL, value);
1059 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL, value);
1673 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
1674 REG_RMW_FIELD(a
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H A Dhw.c769 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
776 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
787 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
893 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
909 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
910 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1335 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1412 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1413 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1417 REG_RMW_FIELD(a
[all...]
H A Dar9002_hw.c538 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
H A Dar9002_phy.c132 REG_RMW_FIELD(ah, AR_AN_SYNTH9,
H A Dhw.h93 #define REG_RMW_FIELD(_a, _r, _f, _v) \ macro

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