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Searched refs:PORT_PREF0 (Results 1 - 9 of 9) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf537/include/mach/
H A D	mem_map.h	51 #define DMEM_CNTR (ACACHE_BSRAM \| ENDCPLB \| PORT_PREF0) 57 #define DMEM_CNTR (ACACHE_BCACHE \| ENDCPLB \| PORT_PREF0) 65 #define DMEM_CNTR (ASRAM_BSRAM \| ENDCPLB \| PORT_PREF0) 87 #define DMEM_CNTR (ACACHE_BSRAM \| ENDCPLB \| PORT_PREF0) 94 #define DMEM_CNTR (ACACHE_BCACHE \| ENDCPLB \| PORT_PREF0) 102 #define DMEM_CNTR (ASRAM_BSRAM \| ENDCPLB \| PORT_PREF0) 123 #define DMEM_CNTR (ACACHE_BSRAM \| ENDCPLB \| PORT_PREF0) 130 #define DMEM_CNTR (ACACHE_BCACHE \| ENDCPLB \| PORT_PREF0) 138 #define DMEM_CNTR (ASRAM_BSRAM \| ENDCPLB \| PORT_PREF0)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf533/include/mach/
H A D	mem_map.h	`54 #define DMEM_CNTR (ACACHE_BSRAM \| ENDCPLB \| PORT_PREF0) 60 #define DMEM_CNTR (ACACHE_BCACHE \| ENDCPLB \| PORT_PREF0) 68 #define DMEM_CNTR (ASRAM_BSRAM \| ENDCPLB \| PORT_PREF0) 92 #define DMEM_CNTR (ACACHE_BSRAM \| ENDCPLB \| PORT_PREF0) 99 #define DMEM_CNTR (ACACHE_BCACHE \| ENDCPLB \| PORT_PREF0) 107 #define DMEM_CNTR (ASRAM_BSRAM \| ENDCPLB \| PORT_PREF0) 126 #define DMEM_CNTR (ACACHE_BSRAM \| ENDCPLB \| PORT_PREF0) 131 #define DMEM_CNTR (ASRAM_BSRAM \| ENDCPLB \| PORT_PREF0)`
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf518/include/mach/
H A D	mem_map.h	`49 #define DMEM_CNTR (ACACHE_BSRAM \| ENDCPLB \| PORT_PREF0) 55 #define DMEM_CNTR (ACACHE_BCACHE \| ENDCPLB \| PORT_PREF0) 63 #define DMEM_CNTR (ASRAM_BSRAM \| ENDCPLB \| PORT_PREF0)`
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf527/include/mach/
H A D	mem_map.h	`49 #define DMEM_CNTR (ACACHE_BSRAM \| ENDCPLB \| PORT_PREF0) 55 #define DMEM_CNTR (ACACHE_BCACHE \| ENDCPLB \| PORT_PREF0) 63 #define DMEM_CNTR (ASRAM_BSRAM \| ENDCPLB \| PORT_PREF0)`
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf538/include/mach/
H A D	mem_map.h	`53 #define DMEM_CNTR (ACACHE_BSRAM \| ENDCPLB \| PORT_PREF0) 59 #define DMEM_CNTR (ACACHE_BCACHE \| ENDCPLB \| PORT_PREF0) 67 #define DMEM_CNTR (ASRAM_BSRAM \| ENDCPLB \| PORT_PREF0)`
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/
H A D	mem_map.h	`53 #define DMEM_CNTR (ACACHE_BSRAM \| ENDCPLB \| PORT_PREF0) 59 #define DMEM_CNTR (ACACHE_BCACHE \| ENDCPLB \| PORT_PREF0) 67 #define DMEM_CNTR (ASRAM_BSRAM \| ENDCPLB \| PORT_PREF0)`
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf561/include/mach/
H A D	mem_map.h	`56 #define DMEM_CNTR (ACACHE_BSRAM \| ENDCPLB \| PORT_PREF0) 62 #define DMEM_CNTR (ACACHE_BCACHE \| ENDCPLB \| PORT_PREF0) 70 #define DMEM_CNTR (ASRAM_BSRAM \| ENDCPLB \| PORT_PREF0)`
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-common/
H A D	cache-c.c	`66 (DMEM_CNTR \| PORT_PREF0 \| (ANOMALY_05000287 ? PORT_PREF1 : 0)));`
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/include/asm/
H A D	def_LPBlackfin.h	`545 #define PORT_PREF0 0x00001000 /* DAG0 Port Preference */ macro`

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