Searched refs:PLL_WR_EN (Results 1 - 7 of 7) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/aty/
H A Dmach64_ct.c36 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) | PLL_WR_EN, par);
39 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) & ~PLL_WR_EN, par);
H A Dradeonfb.h447 tmp = save & ~(0x3f | PLL_WR_EN);
H A Dradeon_pm.c1478 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
1513 OUTREG8(CLOCK_CNTL_INDEX, pllMPLL_CNTL + PLL_WR_EN);
1634 OUTREG8(CLOCK_CNTL_INDEX, pllHTOTAL_CNTL + PLL_WR_EN);
1652 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
H A Daty128fb.c539 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/include/video/
H A Daty128.h239 #define PLL_WR_EN 0x00000080 macro
H A Dmach64.h140 #define PLL_WR_EN 0x02 macro
H A Dradeon.h510 #define PLL_WR_EN 0x00000080 macro

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