Searched refs:PLL_DIV (Results 1 - 16 of 16) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/mips/ar7/
H A Dclock.c67 #define PLL_DIV 0x00000002 macro
205 if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-common/
H A Ddpmc_modes.S92 P0.H = hi(PLL_DIV);
93 P0.L = lo(PLL_DIV);
155 P0.H = hi(PLL_DIV);
156 P0.L = lo(PLL_DIV);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h25 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
26 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
H A DdefBF532.h21 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF51x_base.h21 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
22 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
H A DdefBF51x_base.h17 #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF52x_base.h21 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
22 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
H A DdefBF52x_base.h19 #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h18 #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ macro
H A DcdefBF534.h20 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
21 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf561/include/mach/
H A DdefBF561.h24 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ macro
H A DcdefBF561.h24 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
25 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h21 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
22 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
H A DdefBF539.h21 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h18 #define PLL_DIV 0xffc00004 /* PLL Divisor Register */ macro
H A DcdefBF54x_base.h21 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
22 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)

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