Searched refs:PLL_CTL (Results 1 - 19 of 19) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/include/asm/
H A Ddpmc.h12 /* PLL_CTL Masks */
143 R0 = [P0 + (x - PLL_CTL)];\
148 [P0 + (x - PLL_CTL)] = R0;\
151 R0 = w[P0 + (x - PLL_CTL)];\
156 w[P0 + (x - PLL_CTL)] = R0;\
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/sound/pci/ctxfi/
H A Dct20k2reg.h32 #define PLL_CTL 0x1B7080 macro
H A Dcthw20k2.c1304 hw_write_20kx(hw, PLL_CTL, pllctl);
1306 pllctl = hw_read_20kx(hw, PLL_CTL);
1315 hw_write_20kx(hw, PLL_CTL, pllctl);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-common/
H A Dclocks-init.c76 /* We always write PLL_CTL thus avoiding Anomaly 05000242 */
77 bfin_write16(PLL_CTL, PLL_CTL_VAL);
H A Ddpmc_modes.S20 P0.H = hi(PLL_CTL);
21 P0.L = lo(PLL_CTL);
39 P0.H = hi(PLL_CTL);
40 P0.L = lo(PLL_CTL);
98 P0.H = hi(PLL_CTL);
99 P0.L = lo(PLL_CTL);
130 P0.H = hi(PLL_CTL);
131 P0.L = lo(PLL_CTL);
159 P0.H = hi(PLL_CTL);
160 P0.L = lo(PLL_CTL);
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h19 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
700 /* Writing to PLL_CTL initiates a PLL relock sequence. */
714 bfin_write16(PLL_CTL, val);
H A DdefBF532.h20 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF51x_base.h20 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
1061 /* Writing to PLL_CTL initiates a PLL relock sequence. */
1077 bfin_write16(PLL_CTL, val);
H A DdefBF51x_base.h16 #define PLL_CTL 0xFFC00000 /* PLL Control Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF52x_base.h20 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
1113 /* Writing to PLL_CTL initiates a PLL relock sequence. */
1129 bfin_write16(PLL_CTL, val);
H A DdefBF52x_base.h18 #define PLL_CTL 0xFFC00000 /* PLL Control Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h17 #define PLL_CTL 0xFFC00000 /* PLL Control Register */ macro
H A DcdefBF534.h19 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
1753 /* Writing to PLL_CTL initiates a PLL relock sequence. */
1767 bfin_write16(PLL_CTL, val);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf561/include/mach/
H A DdefBF561.h23 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ macro
H A DcdefBF561.h23 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
1537 /* Writing to PLL_CTL initiates a PLL relock sequence. */
1553 bfin_write16(PLL_CTL, val);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h20 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
2030 /* Writing to PLL_CTL initiates a PLL relock sequence. */
2046 bfin_write16(PLL_CTL, val);
H A DdefBF539.h20 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h17 #define PLL_CTL 0xffc00000 /* PLL Control Register */ macro
H A DcdefBF54x_base.h20 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
2651 /* Writing to PLL_CTL initiates a PLL relock sequence. */
2669 bfin_write16(PLL_CTL, val);

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