Searched refs:NV_RD32 (Results 1 - 10 of 10) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/riva/
H A Dnv_driver.c60 reg52C = NV_RD32(PRAMDAC, 0x052C);
61 reg608 = NV_RD32(PRAMDAC, 0x0608);
67 NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
74 present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? TRUE : FALSE;
77 NV_RD32(par->riva.PRAMDAC0, 0x0608) & 0x0000EFFF);
139 if (NV_RD32(par->riva.PRAMDAC0, 0x0000052C) & 0x100)
145 if(NV_RD32(par->riva.PRAMDAC0, 0x0000252C) & 0x100)
165 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) {
166 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
167 && ((NV_RD32(chi
[all...]
H A Driva_hw.c65 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
66 NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01);
73 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
74 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01);
81 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
82 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01);
622 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
629 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
811 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
814 pll = NV_RD32(
[all...]
H A Driva_hw.h83 #define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i))) macro
558 (hwinst).FifoFreeCount = NV_RD32(&(hwinst).hwptr->FifoFree, 0) >> 2; \
H A Dfbdev.c316 tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF;
317 tmp_pcrt = NV_RD32(par->riva.PCRTC0, 0x081C) & 0xFFFFFFFC;
802 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
809 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
811 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
817 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
819 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
822 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/nvidia/
H A Dnv_hw.c83 NV_WR32(par->PRAMDAC, 0x0300, NV_RD32(par->PRAMDAC, 0x0300));
147 pll = NV_RD32(par->PMC, 0x4020);
149 pll = NV_RD32(par->PMC, 0x4024);
162 pll = NV_RD32(par->PMC, 0x4000);
164 pll = NV_RD32(par->PMC, 0x4004);
172 pll = NV_RD32(par->PRAMDAC0, 0x0504);
176 pll = NV_RD32(par->PRAMDAC0, 0x0574);
186 pll = NV_RD32(par->PRAMDAC0, 0x0500);
190 pll = NV_RD32(par->PRAMDAC0, 0x0570);
202 pll = NV_RD32(pa
[all...]
H A Dnv_setup.c150 dac0_reg608 = NV_RD32(PRAMDAC, 0x0608);
154 reg52C = NV_RD32(PRAMDAC, 0x052C);
155 reg608 = NV_RD32(PRAMDAC, 0x0608);
161 NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
164 NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) |
169 present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? 1 : 0;
202 if (NV_RD32(par->PFB, 0x0000) & 0x00000100) {
204 ((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 +
207 switch (NV_RD32(par->PFB, 0x0000) & 0x00000003) {
223 par->CrystalFreqKHz = (NV_RD32(pa
[all...]
H A Dnv_backlight.c66 tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF;
67 tmp_pcrt = NV_RD32(par->PCRTC0, 0x081C) & 0xFFFFFFFC;
68 fpcontrol = NV_RD32(par->PRAMDAC, 0x0848) & 0xCFFFFFCC;
H A Dnv_local.h67 #define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i))) macro
96 #define READ_GET(par) (NV_RD32(&(par)->FIFO[0x0011], 0) >> 2)
H A Dnvidia.c426 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
436 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
452 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
453 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
456 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
458 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
460 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
461 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
463 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
465 state->vpll2B = NV_RD32(pa
[all...]
H A Dnv_accel.c99 while (--count && NV_RD32(par->PGRAPH, 0x0700)) ;

Completed in 139 milliseconds