/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/sh/kernel/cpu/sh4a/ |
H A D | hwblk-sh7722.c | 29 #define MSTPCR0 0xa4150030 macro 43 [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA), 44 [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA), 45 [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA), 46 [HWBLK_URAM] = HWBLK(MSTPCR0, 28, CORE_AREA), 47 [HWBLK_XYMEM] = HWBLK(MSTPCR0, 26, CORE_AREA), 48 [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA), 49 [HWBLK_DMAC] = HWBLK(MSTPCR0, 21, CORE_AREA_BM), 50 [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA), 51 [HWBLK_HUDI] = HWBLK(MSTPCR0, 1 [all...] |
H A D | hwblk-sh7723.c | 29 #define MSTPCR0 0xa4150030 macro 43 [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA), 44 [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA), 45 [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA), 46 [HWBLK_L2C] = HWBLK(MSTPCR0, 28, CORE_AREA), 47 [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA), 48 [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA), 49 [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA), 50 [HWBLK_DMAC0] = HWBLK(MSTPCR0, 21, CORE_AREA_BM), 51 [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 2 [all...] |
H A D | hwblk-sh7724.c | 29 #define MSTPCR0 0xa4150030 macro 43 [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA), 44 [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA), 45 [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA), 46 [HWBLK_RSMEM] = HWBLK(MSTPCR0, 28, CORE_AREA), 47 [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA), 48 [HWBLK_L2C] = HWBLK(MSTPCR0, 26, CORE_AREA), 49 [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA), 50 [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA), 51 [HWBLK_DMAC0] = HWBLK(MSTPCR0, 2 [all...] |
H A D | clock-sh7786.c | 82 #define MSTPCR0 0xffc40030 macro 94 /* MSTPCR0 */ 95 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), 96 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), 97 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), 98 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), 99 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), 100 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), 101 [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), 102 [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2 [all...] |
H A D | clock-sh7785.c | 83 #define MSTPCR0 0xffc80030 macro 93 /* MSTPCR0 */ 94 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), 95 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), 96 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), 97 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), 98 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), 99 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), 100 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), 101 [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2 [all...] |
H A D | clock-sh7366.c | 33 #define MSTPCR0 0xa4150030 macro 154 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), 155 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), 156 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), 157 [MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 158 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 159 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0), 160 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0), 161 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0), 162 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2 [all...] |
H A D | clock-sh7343.c | 33 #define MSTPCR0 0xa4150030 macro 151 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), 152 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), 153 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), 154 [MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 155 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 156 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0), 157 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0), 158 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0), 159 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2 [all...] |
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/sh/include/cpu-sh4/cpu/ |
H A D | freq.h | 20 #define MSTPCR0 0xa4150030 macro 44 #define MSTPCR0 0xa4150030 macro
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