• Home
  • History
  • Annotate
  • Line#
  • Navigate
  • Raw
  • Download
  • only in /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/sh/include/cpu-sh4/cpu/
1/*
2 * include/asm-sh/cpu-sh4/freq.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License.  See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_FREQ_H
11#define __ASM_CPU_SH4_FREQ_H
12
13#if defined(CONFIG_CPU_SUBTYPE_SH7722) || defined(CONFIG_CPU_SUBTYPE_SH7723) || \
14	defined(CONFIG_CPU_SUBTYPE_SH7343) || defined(CONFIG_CPU_SUBTYPE_SH7366)
15#define FRQCR		        0xa4150000
16#define VCLKCR			0xa4150004
17#define SCLKACR			0xa4150008
18#define SCLKBCR			0xa415000c
19#define IrDACLKCR		0xa4150010
20#define MSTPCR0			0xa4150030
21#define MSTPCR1			0xa4150034
22#define MSTPCR2			0xa4150038
23#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
24#define	FRQCR			0xffc80000
25#define	OSCCR			0xffc80018
26#define	PLLCR			0xffc80024
27#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
28      defined(CONFIG_CPU_SUBTYPE_SH7780)
29#define	FRQCR			0xffc80000
30#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
31#define FRQCRA			0xa4150000
32#define FRQCRB			0xa4150004
33#define VCLKCR			0xa4150048
34
35#define FCLKACR			0xa4150008
36#define FCLKBCR			0xa415000c
37#define FRQCR			FRQCRA
38#define SCLKACR			FCLKACR
39#define SCLKBCR			FCLKBCR
40#define FCLKACR			0xa4150008
41#define FCLKBCR			0xa415000c
42#define IrDACLKCR		0xa4150018
43
44#define MSTPCR0			0xa4150030
45#define MSTPCR1			0xa4150034
46#define MSTPCR2			0xa4150038
47
48#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
49#define FRQCR0			0xffc80000
50#define FRQCR1			0xffc80004
51#define FRQMR1			0xffc80014
52#elif defined(CONFIG_CPU_SUBTYPE_SH7786)
53#define FRQCR0			0xffc40000
54#define FRQCR1			0xffc40004
55#define FRQMR1			0xffc40014
56#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
57#define FRQCR			0xffc00014
58#else
59#define FRQCR			0xffc00000
60#define FRQCR_PSTBY		0x0200
61#define FRQCR_PLLEN		0x0400
62#define FRQCR_CKOEN		0x0800
63#endif
64#define MIN_DIVISOR_NR		0
65#define MAX_DIVISOR_NR		3
66
67#endif /* __ASM_CPU_SH4_FREQ_H */
68