Searched refs:EPPI0_CLKDIV (Results 1 - 4 of 4) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/
H A DdefBF544.h50 #define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */ macro
H A DcdefBF544.h75 #define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
76 #define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
H A DcdefBF547.h122 #define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
123 #define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
H A DdefBF547.h75 #define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */ macro

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