Searched refs:EBIU_SDRRC (Results 1 - 12 of 12) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h449 #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
450 #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
H A DdefBF532.h178 #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF51x_base.h373 #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
374 #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
H A DdefBF51x_base.h214 #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF52x_base.h390 #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
391 #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
H A DdefBF52x_base.h213 #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h192 #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ macro
H A DcdefBF534.h352 #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
353 #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf561/include/mach/
H A DdefBF561.h299 #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ macro
H A DcdefBF561.h505 #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
506 #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h486 #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
487 #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
H A DdefBF539.h192 #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ macro

Completed in 202 milliseconds