Searched refs:EBIU_AMBCTL1 (Results 1 - 15 of 15) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-common/
H A Ddpmc_modes.S374 PM_SYS_PUSH(EBIU_AMBCTL1)
731 PM_SYS_POP(EBIU_AMBCTL1)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h443 #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
444 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
H A DdefBF532.h172 #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF51x_base.h367 #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
368 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
H A DdefBF51x_base.h211 #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ macro
973 /* EBIU_AMBCTL1 Masks */
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF52x_base.h384 #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
385 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
H A DdefBF52x_base.h210 #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ macro
982 /* EBIU_AMBCTL1 Masks */
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h154 #define EBIU_AMBCTL1 0xffc00a08 /* Asynchronous Memory Bank Control Register */ macro
1662 /* Bit masks for EBIU_AMBCTL1 */
2757 #define EBIU_AMCBCTL1 EBIU_AMBCTL1
H A DcdefBF54x_base.h219 #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
220 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h189 #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ macro
1344 /* EBIU_AMBCTL1 Masks */
H A DcdefBF534.h346 #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
347 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf561/include/mach/
H A DdefBF561.h294 #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ macro
H A DcdefBF561.h498 #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
499 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h480 #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
481 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
H A DdefBF539.h187 #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ macro
2075 /* EBIU_AMBCTL1 Masks */

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