Searched refs:EBIU_AMBCTL0 (Results 1 - 15 of 15) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-common/
H A Ddpmc_modes.S373 PM_SYS_PUSH(EBIU_AMBCTL0)
732 PM_SYS_POP(EBIU_AMBCTL0)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h441 #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
442 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
H A DdefBF532.h171 #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF51x_base.h365 #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
366 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
H A DdefBF51x_base.h210 #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ macro
882 /* EBIU_AMBCTL0 Masks */
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF52x_base.h382 #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
383 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
H A DdefBF52x_base.h209 #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ macro
891 /* EBIU_AMBCTL0 Masks */
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h153 #define EBIU_AMBCTL0 0xffc00a04 /* Asynchronous Memory Bank Control Register */ macro
1645 /* Bit masks for EBIU_AMBCTL0 */
2756 #define EBIU_AMCBCTL0 EBIU_AMBCTL0
H A DcdefBF54x_base.h217 #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
218 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h188 #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ macro
1253 /* EBIU_AMBCTL0 Masks */
H A DcdefBF534.h344 #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
345 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf561/include/mach/
H A DdefBF561.h293 #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ macro
H A DcdefBF561.h496 #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
497 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h478 #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
479 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
H A DdefBF539.h186 #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ macro
1985 /* EBIU_AMBCTL0 Masks */

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