Searched refs:DMA3_CONFIG (Results 1 - 12 of 12) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h195 #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
196 #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
H A DdefBF532.h232 #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF51x_base.h473 #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
474 #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
H A DdefBF51x_base.h270 #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF52x_base.h490 #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
491 #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
H A DdefBF52x_base.h270 #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h248 #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ macro
H A DcdefBF534.h451 #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
452 #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h576 #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
577 #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
H A DdefBF539.h253 #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h256 #define DMA3_CONFIG 0xffc00cc8 /* DMA Channel 3 Configuration Register */ macro
H A DcdefBF54x_base.h402 #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
403 #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)

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