Searched refs:DMA0_START_ADDR (Results 1 - 12 of 12) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h118 #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
119 #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
H A DdefBF532.h192 #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF51x_base.h396 #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
397 #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
H A DdefBF51x_base.h227 #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF52x_base.h413 #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
414 #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
H A DdefBF52x_base.h227 #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h205 #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ macro
H A DcdefBF534.h374 #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
375 #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h496 #define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
497 #define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
H A DdefBF539.h210 #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h207 #define DMA0_START_ADDR 0xffc00c04 /* DMA Channel 0 Start Address Register */ macro
H A DcdefBF54x_base.h313 #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
314 #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)

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