Searched refs:CPU_REG (Results 1 - 6 of 6) sorted by relevance
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-h720x/include/mach/ |
H A D | system.h | 19 CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE; 22 CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN; 30 CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET;
|
H A D | hardware.h | 42 #define CPU_REG(x,y) CPU_IO(x+y) macro 45 #define IRQ_REG(x) CPU_REG(IRQC_VIRT,x)
|
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-h720x/ |
H A D | cpu-h7201.c | 32 CPU_REG (TIMER_VIRT, TIMER_TOPSTAT); 49 CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH; 50 CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET; 51 CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START; 52 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT;
|
H A D | cpu-h7202.c | 113 mask = CPU_REG (TIMER_VIRT, TIMER_TOPSTAT); 148 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit; 158 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit; 178 CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH; 179 CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET; 180 CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START; 181 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT; 195 CPU_REG (GPIO_E_VIRT, GPIO_MASK) = 0x0; 212 CPU_REG (PMU_BASE, PMU_PLL_CTRL) |= PLL_2_EN | PLL_1_EN | PLL_3_MUTE; 214 CPU_REG (SERIAL0_VIR [all...] |
H A D | common.c | 45 return (CPU_REG (TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH; 53 CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << irq); 61 CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << irq); 73 if ( (CPU_REG (reg_base, GPIO_EDGE) & bit)) 74 CPU_REG (reg_base, GPIO_CLR) = bit; 84 CPU_REG (reg_base, GPIO_MASK) &= ~bit; 94 CPU_REG (reg_base, GPIO_MASK) |= bit; 117 mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT); 127 mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT); 138 mask = CPU_REG(GPIO_C_VIR [all...] |
H A D | h7202-eval.c | 69 CPU_REG (GPIO_B_VIRT, GPIO_POL) &= ~(1 << 8); 70 CPU_REG (GPIO_B_VIRT, GPIO_EN) |= (1 << 8);
|
Completed in 32 milliseconds