1/* 2 * linux/arch/arm/mach-h720x/common.c 3 * 4 * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de> 5 * 2003 Robert Schwebel <r.schwebel@pengutronix.de> 6 * 2004 Sascha Hauer <s.hauer@pengutronix.de> 7 * 8 * common stuff for Hynix h720x processors 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 */ 15 16#include <linux/sched.h> 17#include <linux/mman.h> 18#include <linux/init.h> 19#include <linux/interrupt.h> 20#include <linux/io.h> 21 22#include <asm/page.h> 23#include <asm/pgtable.h> 24#include <asm/dma.h> 25#include <mach/hardware.h> 26#include <asm/irq.h> 27#include <asm/mach/irq.h> 28#include <asm/mach/map.h> 29#include <mach/irqs.h> 30 31#include <asm/mach/dma.h> 32 33#define IRQDBG(args...) do {} while(0) 34 35void __init arch_dma_init(dma_t *dma) 36{ 37} 38 39/* 40 * Return usecs since last timer reload 41 * (timercount * (usecs perjiffie)) / (ticks per jiffie) 42 */ 43unsigned long h720x_gettimeoffset(void) 44{ 45 return (CPU_REG (TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH; 46} 47 48/* 49 * mask Global irq's 50 */ 51static void mask_global_irq (unsigned int irq ) 52{ 53 CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << irq); 54} 55 56/* 57 * unmask Global irq's 58 */ 59static void unmask_global_irq (unsigned int irq ) 60{ 61 CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << irq); 62} 63 64 65/* 66 * ack GPIO irq's 67 * Ack only for edge triggered int's valid 68 */ 69static void inline ack_gpio_irq(u32 irq) 70{ 71 u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq)); 72 u32 bit = IRQ_TO_BIT(irq); 73 if ( (CPU_REG (reg_base, GPIO_EDGE) & bit)) 74 CPU_REG (reg_base, GPIO_CLR) = bit; 75} 76 77/* 78 * mask GPIO irq's 79 */ 80static void inline mask_gpio_irq(u32 irq) 81{ 82 u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq)); 83 u32 bit = IRQ_TO_BIT(irq); 84 CPU_REG (reg_base, GPIO_MASK) &= ~bit; 85} 86 87/* 88 * unmask GPIO irq's 89 */ 90static void inline unmask_gpio_irq(u32 irq) 91{ 92 u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq)); 93 u32 bit = IRQ_TO_BIT(irq); 94 CPU_REG (reg_base, GPIO_MASK) |= bit; 95} 96 97static void 98h720x_gpio_handler(unsigned int mask, unsigned int irq, 99 struct irq_desc *desc) 100{ 101 IRQDBG("%s irq: %d\n", __func__, irq); 102 while (mask) { 103 if (mask & 1) { 104 IRQDBG("handling irq %d\n", irq); 105 generic_handle_irq(irq); 106 } 107 irq++; 108 mask >>= 1; 109 } 110} 111 112static void 113h720x_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc) 114{ 115 unsigned int mask, irq; 116 117 mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT); 118 irq = IRQ_CHAINED_GPIOA(0); 119 IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq); 120 h720x_gpio_handler(mask, irq, desc); 121} 122 123static void 124h720x_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc) 125{ 126 unsigned int mask, irq; 127 mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT); 128 irq = IRQ_CHAINED_GPIOB(0); 129 IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq); 130 h720x_gpio_handler(mask, irq, desc); 131} 132 133static void 134h720x_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc) 135{ 136 unsigned int mask, irq; 137 138 mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT); 139 irq = IRQ_CHAINED_GPIOC(0); 140 IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq); 141 h720x_gpio_handler(mask, irq, desc); 142} 143 144static void 145h720x_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc) 146{ 147 unsigned int mask, irq; 148 149 mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT); 150 irq = IRQ_CHAINED_GPIOD(0); 151 IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq); 152 h720x_gpio_handler(mask, irq, desc); 153} 154 155#ifdef CONFIG_CPU_H7202 156static void 157h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc) 158{ 159 unsigned int mask, irq; 160 161 mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT); 162 irq = IRQ_CHAINED_GPIOE(0); 163 IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq); 164 h720x_gpio_handler(mask, irq, desc); 165} 166#endif 167 168static struct irq_chip h720x_global_chip = { 169 .ack = mask_global_irq, 170 .mask = mask_global_irq, 171 .unmask = unmask_global_irq, 172}; 173 174static struct irq_chip h720x_gpio_chip = { 175 .ack = ack_gpio_irq, 176 .mask = mask_gpio_irq, 177 .unmask = unmask_gpio_irq, 178}; 179 180/* 181 * Initialize IRQ's, mask all, enable multiplexed irq's 182 */ 183void __init h720x_init_irq (void) 184{ 185 int irq; 186 187 /* Mask global irq's */ 188 CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0; 189 190 /* Mask all multiplexed irq's */ 191 CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0; 192 CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0; 193 CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0; 194 CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0; 195 196 /* Initialize global IRQ's, fast path */ 197 for (irq = 0; irq < NR_GLBL_IRQS; irq++) { 198 set_irq_chip(irq, &h720x_global_chip); 199 set_irq_handler(irq, handle_level_irq); 200 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 201 } 202 203 /* Initialize multiplexed IRQ's, slow path */ 204 for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) { 205 set_irq_chip(irq, &h720x_gpio_chip); 206 set_irq_handler(irq, handle_edge_irq); 207 set_irq_flags(irq, IRQF_VALID ); 208 } 209 set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler); 210 set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler); 211 set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler); 212 set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler); 213 214#ifdef CONFIG_CPU_H7202 215 for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) { 216 set_irq_chip(irq, &h720x_gpio_chip); 217 set_irq_handler(irq, handle_edge_irq); 218 set_irq_flags(irq, IRQF_VALID ); 219 } 220 set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler); 221#endif 222 223 /* Enable multiplexed irq's */ 224 CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX; 225} 226 227static struct map_desc h720x_io_desc[] __initdata = { 228 { 229 .virtual = IO_VIRT, 230 .pfn = __phys_to_pfn(IO_PHYS), 231 .length = IO_SIZE, 232 .type = MT_DEVICE 233 }, 234}; 235 236/* Initialize io tables */ 237void __init h720x_map_io(void) 238{ 239 iotable_init(h720x_io_desc,ARRAY_SIZE(h720x_io_desc)); 240} 241