Searched refs:CLOCK_CNTL (Results 1 - 4 of 4) sorted by relevance
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/aty/ |
H A D | mach64_gx.c | 58 tmp = aty_ld_8(CLOCK_CNTL, par); 59 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, tmp | CLOCK_STROBE, par); 406 tmp = aty_ld_8(CLOCK_CNTL, par); 407 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 410 tmp = aty_ld_8(CLOCK_CNTL, par); 411 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, (tmp & ~0x08) | (0 << 3), 416 tmp = aty_ld_8(CLOCK_CNTL, par); 417 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, (tmp & ~0x08) | (1 << 3), 436 old_clock_cntl = aty_ld_8(CLOCK_CNTL, par); 437 aty_st_8(CLOCK_CNTL [all...] |
H A D | mach64_ct.c | 304 aty_st_8(CLOCK_CNTL, par->clk_wr_offset | CLOCK_STROBE, par); 381 clock = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
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H A D | atyfb_base.c | 2551 "DSP_ON_OFF CLOCK_CNTL\n" 2563 aty_ld_le32(CLOCK_CNTL, par)); 3087 clock_cntl = aty_ld_8(CLOCK_CNTL, par); 3088 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */ 3098 * PLL Feedback Divider N (Dependant on CLOCK_CNTL): 3103 * PLL Post Divider P (Dependant on CLOCK_CNTL): 3482 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U; 3644 aty_st_le32(CLOCK_CNTL, 0x12345678, par); 3645 clock_r = aty_ld_le32(CLOCK_CNTL, par);
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/include/video/ |
H A D | mach64.h | 121 #define CLOCK_CNTL 0x0090 /* Dword offset 0_24 */ macro 122 /* CLOCK_CNTL register constants CT LAYOUT */ 132 /* CLOCK_CNTL register constants GX LAYOUT */ 139 #define CLOCK_CNTL_ADDR CLOCK_CNTL + 1 142 #define CLOCK_CNTL_DATA CLOCK_CNTL + 2
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