Searched refs:AR5K_REG_ENABLE_BITS (Results 1 - 12 of 12) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/net/wireless/ath/ath5k/
H A Dgpio.c73 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led);
75 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led_5210);
167 AR5K_REG_ENABLE_BITS(ah, AR5K_PIMR, AR5K_IMR_GPIO);
H A Dqcu.c328 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
332 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
337 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
346 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
349 AR5K_REG_ENABLE_BITS(ah,
369 AR5K_REG_ENABLE_BITS(ah,
387 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
392 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
401 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
413 AR5K_REG_ENABLE_BITS(a
[all...]
H A Dcaps.c175 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
H A Dpcu.c69 AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
157 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
393 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
468 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
591 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM);
H A Dreset.c566 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
711 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
848 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1060 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
1109 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
1234 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1244 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
H A Dattach.c262 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX);
323 AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
H A Dphy.c1077 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1080 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1225 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1249 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1259 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1299 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1309 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1387 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1393 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
1581 AR5K_REG_ENABLE_BITS(a
[all...]
H A Ddma.c237 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
H A Dani.c168 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR,
H A Deeprom.c42 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
46 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
H A Dath5k.h122 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ macro
H A Ddebug.c263 AR5K_REG_ENABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);

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