Searched refs:vMPLL_SS2 (Results 1 - 17 of 17) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/
H A Drv770_smc.h57 uint32_t vMPLL_SS2; member in struct:RV770_SMC_MCLK_VALUE
72 uint32_t vMPLL_SS2; member in struct:RV730_SMC_MCLK_VALUE
H A Dnislands_smc.h83 uint32_t vMPLL_SS2; member in struct:NISLANDS_SMC_MCLK_VALUE
H A Dradeon_rv730_dpm.c197 mclk->mclk730.vMPLL_SS2 = cpu_to_be32(mpll_ss2);
343 table->initialState.levels[0].mclk.mclk730.vMPLL_SS2 =
H A Dsislands_smc.h128 uint32_t vMPLL_SS2; member in struct:SISLANDS_SMC_MCLK_VALUE
H A Dradeon_rv740_dpm.c284 mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2);
H A Dradeon_cypress_dpm.c611 mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2);
1264 table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 =
H A Dradeon_rv770_dpm.c1050 table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 =
H A Dradeon_ni_dpm.c1710 table->initialState.levels[0].mclk.vMPLL_SS2 =
2293 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
H A Dradeon_si_dpm.c4396 table->initialState.levels[0].mclk.vMPLL_SS2 =
4598 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4960 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Dsmu7_hwmgr.h129 uint32_t vMPLL_SS2; member in struct:smu7_clock_registers
H A Damdgpu_smu7_hwmgr.c4315 data->clock_registers.vMPLL_SS2 =
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Dsislands_smc.h128 uint32_t vMPLL_SS2; member in struct:SISLANDS_SMC_MCLK_VALUE
H A Dsi_dpm.h388 uint32_t vMPLL_SS2; member in struct:RV770_SMC_MCLK_VALUE
403 uint32_t vMPLL_SS2; member in struct:RV730_SMC_MCLK_VALUE
734 uint32_t vMPLL_SS2; member in struct:NISLANDS_SMC_MCLK_VALUE
H A Damdgpu_si_dpm.c4862 table->initialState.levels[0].mclk.vMPLL_SS2 =
5063 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
5424 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Damdgpu_iceland_smumgr.c1067 uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
1550 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
H A Damdgpu_ci_smumgr.c1043 uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
1502 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
H A Damdgpu_tonga_smumgr.c810 uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
1292 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);

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