/netbsd-current/sys/arch/powerpc/include/ibm4xx/ |
H A D | Makefile | 5 INCS= cpu.h pmap.h spr.h tlb.h
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H A D | pmap.h | 80 #include <powerpc/ibm4xx/tlb.h>
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/netbsd-current/sys/arch/mips/mips/ |
H A D | wired_map.c | 93 struct tlbmask tlb; local 148 tlb.tlb_mask = mips3_wired_map[index].pgmask; 149 tlb.tlb_hi = mips3_vad_to_vpn(va0); 151 tlb.tlb_lo0 = MIPS3_PG_G; 153 tlb.tlb_lo0 = 158 tlb.tlb_lo1 = MIPS3_PG_G; 160 tlb.tlb_lo1 = mips3_paddr_to_tlbpfn( 164 tlb_write_entry(MIPS3_TLB_WIRED_UPAGES + index, &tlb);
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H A D | db_interface.c | 261 struct tlbmask tlb; local 272 tlb_read_entry(i, &tlb); 273 if (valid_only && !(tlb.tlb_lo1 & MIPS1_PG_V)) 276 (tlb.tlb_lo1 & MIPS1_PG_V) ? ' ' : '*', 277 i, tlb.tlb_hi, 278 tlb.tlb_lo1 & MIPS1_PG_FRAME); 280 (tlb.tlb_lo1 & MIPS1_PG_D) ? 'D' : ' ', 281 (tlb.tlb_lo1 & MIPS1_PG_G) ? 'G' : ' ', 282 (tlb.tlb_lo1 & MIPS1_PG_N) ? 'N' : ' '); 293 tlb_read_entry(i, &tlb); [all...] |
/netbsd-current/sys/arch/emips/emips/ |
H A D | xs_bee3.c | 118 struct tlbmask tlb; local 120 tlb.tlb_hi = USART_DEFAULT_ADDRESS; 121 tlb.tlb_lo0 = USART_DEFAULT_ADDRESS | 0xf02; 122 tlb_write_entry(3, &tlb);
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H A D | interrupt.c | 80 struct tlbmask tlb; local 85 tlb.tlb_hi = INTERRUPT_CONTROLLER_DEFAULT_ADDRESS; 86 tlb.tlb_lo0 = INTERRUPT_CONTROLLER_DEFAULT_ADDRESS | 0xf02; 87 tlb_write_entry(4, &tlb); 89 tlb.tlb_hi = TIMER_DEFAULT_ADDRESS; 90 tlb.tlb_lo0 = TIMER_DEFAULT_ADDRESS | 0xf02; 91 tlb_write_entry(5, &tlb);
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H A D | xilinx_ml40x.c | 121 struct tlbmask tlb; local 123 tlb.tlb_hi = USART_DEFAULT_ADDRESS; 124 tlb.tlb_lo0 = USART_DEFAULT_ADDRESS | 0xf02; 125 tlb_write_entry(3, &tlb);
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/netbsd-current/sys/arch/arm/arm/ |
H A D | cpufunc_asm_fa526.S | 38 cmp r1, #0 @ need to flush the cache / tlb? 225 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
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H A D | cpufunc_asm_armv7.S | 68 mcr p15, 0, r0, c8, c7, 2 @ flush I+D tlb all ASID 76 mcr p15, 0, r0, c8, c3, 2 @ flush I+D tlb all ASID 88 mcr p15, 0, r0, c8, c7, 1 @ flush I+D tlb single entry 91 mcr p15, 0, r0, c8, c7, 1 @ flush I+D tlb single entry 103 mcr p15, 0, r0, c8, c3, 1 @ flush I+D tlb single entry 106 mcr p15, 0, r0, c8, c3, 1 @ flush I+D tlb single entry 119 mcr p15, 0, r0, c8, c6, 0 @ flush entire D tlb 129 mcr p15, 0, r0, c8, c7, 0 @ flush entire I+D tlb 141 mcr p15, 0, r0, c8, c3, 0 @ flush entire I+D tlb, IS
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/netbsd-current/sys/arch/hppa/include/ |
H A D | pte.h | 35 #define PTE_PROT(tlb) ((tlb) >> PTE_PROT_SHIFT)
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/netbsd-current/sys/arch/ews4800mips/stand/common/ |
H A D | cop0.c | 39 struct tlb { struct 48 static void __tlb_pagemask(struct tlb *); 72 struct tlb *e; 99 printf("tlb p entry#.\n"); 143 __tlb_pagemask(struct tlb *e)
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/netbsd-current/sys/arch/powerpc/booke/ |
H A D | booke_stubs.c | 107 tlb_read_entry(size_t pos, struct tlbmask *tlb) argument 109 (*cpu_md_ops.md_tlb_ops->md_tlb_read_entry)(pos, tlb); 115 tlb_write_entry(size_t pos, const struct tlbmask *tlb) argument 117 (*cpu_md_ops.md_tlb_ops->md_tlb_write_entry)(pos, tlb);
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H A D | e500_tlb.c | 110 struct e500_tlb tlb; local 114 tlb.tlb_va = MAS2_EPN & hwtlb.hwtlb_mas2; 115 tlb.tlb_size = 1024 << (2 * MASX_TSIZE_GET(hwtlb.hwtlb_mas1)); 116 tlb.tlb_asid = MASX_TID_GET(hwtlb.hwtlb_mas1); 117 tlb.tlb_pte = (hwtlb.hwtlb_mas2 & MAS2_WIMGE) 126 tlb.tlb_pte |= (prot_mask & hwtlb.hwtlb_mas3) << prot_shift; 127 return tlb; 149 * is less than the number of tlb entries, the slot is split in two 229 tlb_to_hwtlb(const struct e500_tlb tlb) argument 233 KASSERT(trunc_page(tlb 581 e500_tlb_write_entry(size_t index, const struct tlbmask *tlb) argument 586 e500_tlb_read_entry(size_t index, struct tlbmask *tlb) argument 619 struct e500_tlb tlb = hwtlb_to_tlb(hwtlb); local 668 struct e500_tlb tlb = hwtlb_to_tlb(hwtlb); local [all...] |
/netbsd-current/sys/arch/arc/arc/ |
H A D | minidebug.c | 551 printf("tlb-dump\n"); 562 printf("tlb"); 950 struct tlb tlb; local 955 mips3_TLBRead(tlbno, &tlb); 956 if (tlb.tlb_lo0 & MIPS3_PG_V || tlb.tlb_lo1 & MIPS3_PG_V) { 957 printf("TLB %2d vad 0x%08x ", tlbno, tlb.tlb_hi); 959 printf("TLB*%2d vad 0x%08x ", tlbno, tlb.tlb_hi); 961 printf("0=0x%08x ", mips_tlbpfn_to_paddr(tlb [all...] |
/netbsd-current/sys/arch/sparc64/include/ |
H A D | bootinfo.h | 121 struct tlb_entry tlb[1]; member in struct:btinfo_tlb
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/netbsd-current/external/gpl3/gdb.old/dist/gdb/nat/ |
H A D | windows-nat.h | 38 windows_thread_info (DWORD tid_, HANDLE h_, CORE_ADDR tlb) argument 41 thread_local_base (tlb)
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/netbsd-current/sys/arch/usermode/usermode/ |
H A D | pmap.c | 90 static struct pv_entry **tlb; /* current tlb mappings (direct mapped) */ variable in typeref:struct:pv_entry 312 thunk_printf_debug("tlb va->pa lookup table is %"PRIu64" KB for " 337 /* set up tlb space */ 338 tlb = (struct pv_entry **) kmem_kvm_cur_start; 340 addr = thunk_mmap(tlb, pm_entries_size, 344 if (addr != (void *) tlb) 345 panic("pmap_bootstrap: can't map in tlb entries\n"); 347 memset(tlb, 0, pm_entries_size); /* test and clear */ 349 thunk_printf_debug("kernel tlb entrie [all...] |
/netbsd-current/sys/arch/powerpc/include/booke/ |
H A D | cpuvar.h | 117 #include <uvm/pmap/tlb.h>
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/netbsd-current/sys/arch/evbppc/walnut/ |
H A D | machdep.c | 91 #include <powerpc/ibm4xx/tlb.h>
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/netbsd-current/sys/arch/evbppc/obs405/ |
H A D | obs266_machdep.c | 92 #include <powerpc/ibm4xx/tlb.h>
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/netbsd-current/sys/arch/evbppc/explora/ |
H A D | machdep.c | 52 #include <powerpc/ibm4xx/tlb.h>
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/netbsd-current/external/gpl3/binutils.old/dist/gas/ |
H A D | makefile.vms | 68 $(COMPILE.c) /obj=$@ $< + sys$$library:sys$$lib_c.tlb/lib
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/netbsd-current/external/gpl3/binutils/dist/gas/ |
H A D | makefile.vms | 68 $(COMPILE.c) /obj=$@ $< + sys$$library:sys$$lib_c.tlb/lib
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/netbsd-current/external/gpl3/gdb.old/dist/gas/ |
H A D | makefile.vms | 68 $(COMPILE.c) /obj=$@ $< + sys$$library:sys$$lib_c.tlb/lib
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/netbsd-current/external/gpl3/gdb.old/dist/gdb/stubs/ |
H A D | buildvms.com | 20 $cc /debug/noopt /pointer=64 gdbstub +sys$library:sys$lib_c.tlb/lib
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