Add the ARM ARM cache operation name in some comments

branches: 1.27.2;
Do runtime detection of MP extensions to allow using a MULTIPROCESSOR
kernel on CPUs without the MP extensions feature (like Cortex-A8).

Use TTBR_[UM]PATTR in a9_mpsubr.S as well as cpufunc_asm_armv7

Prompted by matt@

Dont use magic number.

No functional change.

Typo in previous

Provide a armv7_dcache_l1inv_all

Add MULTIPROCESSOR tlb flushes to armv7_tlb_flushID. Also, invalidate the
branch predictor.

This function is only used by db_write_bytes and kobj_machdep

branches: 1.21.2;
Ensure all memory operations are complete by before wfi. For example, the
cpu could have just been in uvm_pageidlezero.

Add some dsb instructions to avoid Cortex A7 errata

Don't flush random ASIDs. Instead always assume KERNEL_PID, i.e. 0.
All other TLB flushes are done via

pmap_tlb_invalidate_addr -> tlb_invalidate_addr

OK matt@

branches: 1.18.2;
Remove a leftover _XXX

Address PR/48710.
r3 is not trashed during the routine so the level is preserved.
The only two real bugs was not initializing r3 to 0 to start with L1 cache
and the invalid fetching the set count from r3. The mov r1, #0 should have
been mov r3, #0 and has been corrected.
Instead of two shifts, just use ubfx to extract the set bits and then compare
them to 0.
Add some other minor optimizations that make the code a little clearer.

branches: 1.16.2;
Add ARM_MMU_EXTENDED support

Don't need to round since values are N-1.

Add armv7 versions of tlb routines.

for non-of-power-2 sets, we need to round to next power of 2. (which is
simply doubling the value and then subtracting 1).

branches: 1.12.2;
Move parts of cpu.h that are not needed by MI code in <arm/locore.h>
Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h>
Use <arm/asm.h> instead of <machine/arm.h>

branches: 1.11.2;
Always supply all registers (don't make one implicit).

Implement a "fast" path for IRQ handling out of the idle loop. Since we
are in SVC32 already we only need to save a few registers. Processing is
also simplified since we know we can't return to user-mode.

Add armv7_drain_writebuf (which is just a dsb).

Add a few more DSBs before flushing cache lines.

Fix range ops to properly flush.

Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).

With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.

branches: 1.5.2;
Compute cache line size before doing the loop.
Map translation table for MP with outer-cache=NONE

Enable "shareable" access to the page table for armv7. PTE_SYNC only does
a DSB now on an armv7 cpu and no longer needs to flush the cache line to ram.

Recode armv7_dcache_wbinv_all in asm. Add armv7_dcache_inv_all and
armv7_icache_inv_all as well.
Use dsb/dmb/isb instructions

branches: 1.2.2; 1.2.4; 1.2.6; 1.2.14; 1.2.22;
Cleanup the armv7 changes. Add ARM_ARCH_7. Use CPU_CORTEX instead of
CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8.
CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined.
Add CPU_CORTEXA9 as well. Use .arch armv7a to get us the isb/dsb
instructions.

Test booted to root device prompt on a Beagleboard.
All ARM kernels successfully test built.

PR port-arm/43299: Support added for igepv2/cortexa8/omap3530

Apply patch from PR, with build fixes. ok skrll, matt