Searched refs:smu_clk_type (Results 1 - 12 of 12) sorted by relevance
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
H A D | smu_v12_0.h | 84 enum smu_clk_type clk_id, 87 int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 92 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
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H A D | amdgpu_smu.h | 430 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); 431 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); 433 int (*get_od_percentage)(struct smu_context *smu, enum smu_clk_type clk_type); 435 enum smu_clk_type clk_type, 441 enum smu_clk_type clk_type, 477 enum smu_clk_type clk_type, 486 int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type clk_type, 526 int (*get_current_clk_freq)(struct smu_context *smu, enum smu_clk_type clk_id, uint32_t *value); 567 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); 568 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_typ [all...] |
H A D | smu_v11_0.h | 203 enum smu_clk_type clk_id, 257 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 260 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
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H A D | smu_types.h | 185 enum smu_clk_type { enum
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
H A D | amdgpu_smu_v12_0.c | 360 enum smu_clk_type clk_id, 379 int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 461 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
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H A D | amdgpu_renoir_ppt.c | 230 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, 244 enum smu_clk_type clk_type, char *buf) 395 enum smu_clk_type clk_type, 418 enum smu_clk_type clk_type; 420 enum smu_clk_type clks[] = { 445 enum smu_clk_type clk_type; 448 enum smu_clk_type clk_type; 609 enum smu_clk_type clk_type, uint32_t mask)
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H A D | amdgpu_smu.c | 227 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 242 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 278 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 327 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type, 361 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type, 367 int smu_get_dpm_level_range(struct smu_context *smu, enum smu_clk_type clk_type, 396 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type) 1896 enum smu_clk_type clk_type, 2157 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2171 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type typ [all...] |
H A D | amdgpu_navi10_ppt.c | 716 enum smu_clk_type clk_type, 735 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) 764 enum smu_clk_type clk_type, char *buf) 951 enum smu_clk_type clk_type, uint32_t mask) 1014 enum smu_clk_type clk_type, 1099 enum smu_clk_type clk_type; 1101 enum smu_clk_type clks[] = { 1126 enum smu_clk_type clk_type; 1128 enum smu_clk_type clks[] = {
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H A D | amdgpu_smu_v11_0.c | 940 enum smu_clk_type clock_select) 1123 enum smu_clk_type clk_id, 1321 enum smu_clk_type clk_select = 0; 1769 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 1804 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
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H A D | amdgpu_vega20_ppt.c | 951 enum smu_clk_type type, char *buf) 1282 enum smu_clk_type clk_type, uint32_t mask) 1445 enum smu_clk_type clk_type, 1737 enum smu_clk_type clk_type) 2527 enum smu_clk_type clk_type,
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H A D | amdgpu_arcturus_ppt.c | 622 enum smu_clk_type type, char *buf) 799 enum smu_clk_type type, uint32_t mask) 1068 enum smu_clk_type clk_type,
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm_pp_smu.c | 156 static enum smu_clk_type dc_to_smu_clock_type( 159 enum smu_clk_type smu_clk_type = SMU_CLK_COUNT; local 163 smu_clk_type = SMU_DISPCLK; 166 smu_clk_type = SMU_GFXCLK; 169 smu_clk_type = SMU_MCLK; 172 smu_clk_type = SMU_DCEFCLK; 175 smu_clk_type = SMU_SOCCLK; 183 return smu_clk_type;
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