Searched refs:ref_div (Results 1 - 25 of 28) sorted by relevance

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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_pll.c85 * @ref_div: resulting reference divider
92 unsigned *fb_div, unsigned *ref_div)
98 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
99 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
103 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
119 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
134 unsigned ref_div_min, ref_div_max, ref_div; local
209 ref_div_max, &fb_div, &ref_div);
211 (ref_div * post_di
90 amdgpu_pll_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, unsigned fb_div_max, unsigned ref_div_max, unsigned *fb_div, unsigned *ref_div) argument
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H A Datombios_crtc.h50 u32 ref_div,
H A Damdgpu_atombios_crtc.c343 /* use recommended ref_div for ss */
588 u32 ref_div,
615 args.v1.usRefDiv = cpu_to_le16(ref_div);
625 args.v2.usRefDiv = cpu_to_le16(ref_div);
635 args.v3.usRefDiv = cpu_to_le16(ref_div);
652 args.v5.ucRefDiv = ref_div;
682 args.v6.ucRefDiv = ref_div;
832 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; local
861 &fb_div, &frac_fb_div, &ref_div, &post_div);
868 ref_div, fb_di
582 amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, u32 encoder_mode, u32 encoder_id, u32 clock, u32 ref_div, u32 fb_div, u32 frac_fb_div, u32 post_div, int bpc, bool ss_enabled, struct amdgpu_atom_ss *ss) argument
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H A Damdgpu_atombios.h45 u32 ref_div; member in struct:atom_clock_dividers
H A Damdgpu_atombios.c1037 dividers->ref_div = args.v3.ucRefDiv;
1057 dividers->ref_div = args.v5.ucRefDiv;
1081 dividers->ref_div = args.v6_out.ucPllRefDiv;
H A Dsi_dpm.h573 u32 ref_div; member in struct:rv7xx_power_info
/netbsd-current/sys/arch/mips/atheros/
H A Dar9344.c123 uint32_t out_div, ref_div, nint, post_div; local
141 ref_div = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_REFDIV);
145 const uint32_t cpu_pll_freq = (nint * ref_clk / ref_div) >> out_div;
152 ref_div = __SHIFTOUT(pll, AR9344_DDR_PLL_CONFIG_REFDIV);
156 const uint32_t ddr_pll_freq = (nint * ref_clk / ref_div) >> out_div;
/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_display.c917 * @ref_div: resulting reference divider
924 unsigned *fb_div, unsigned *ref_div)
930 *ref_div = min(max(den/post_div, 1u), ref_div_max);
931 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
935 *ref_div = (*ref_div * fb_div_max)/(*fb_div);
951 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
966 unsigned ref_div_min, ref_div_max, ref_div; local
1044 ref_div_max, &fb_div, &ref_div);
1046 (ref_div * post_di
922 avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, unsigned fb_div_max, unsigned ref_div_max, unsigned *fb_div, unsigned *ref_div) argument
1169 uint32_t ref_div; local
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H A Dradeon_clocks.c48 uint32_t fb_div, ref_div, post_div, sclk; local
55 ref_div =
58 if (ref_div == 0)
61 sclk = fb_div / ref_div;
78 uint32_t fb_div, ref_div, post_div, mclk; local
85 ref_div =
88 if (ref_div == 0)
91 mclk = fb_div / ref_div;
361 int ref_div = spll->reference_div; local
363 if (!ref_div)
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H A Dradeon_rv740_dpm.c146 reference_divider = 1 + dividers.ref_div;
153 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
221 mpll_ad_func_cntl |= CLKR(dividers.ref_div);
238 mpll_dq_func_cntl |= CLKR(dividers.ref_div);
257 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
H A Dradeon_rs780_dpm.c92 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div);
459 if ((min_dividers.ref_div != max_dividers.ref_div) ||
461 (max_dividers.ref_div != current_max_dividers.ref_div) ||
995 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; local
999 (post_div * ref_div);
1018 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; local
1022 (post_div * ref_div);
H A Dradeon_rv730_dpm.c66 reference_divider = 1 + dividers.ref_div;
84 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
144 reference_divider = dividers.ref_div + 1;
159 mpll_func_cntl |= MPLL_REF_DIV(dividers.ref_div);
H A Dradeon_atombios_crtc.c632 /* use recommended ref_div for ss */
834 u32 ref_div,
861 args.v1.usRefDiv = cpu_to_le16(ref_div);
871 args.v2.usRefDiv = cpu_to_le16(ref_div);
881 args.v3.usRefDiv = cpu_to_le16(ref_div);
898 args.v5.ucRefDiv = ref_div;
927 args.v6.ucRefDiv = ref_div;
1077 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; local
1109 &fb_div, &frac_fb_div, &ref_div, &post_div);
1112 &fb_div, &frac_fb_div, &ref_div,
828 atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, u32 encoder_mode, u32 encoder_id, u32 clock, u32 ref_div, u32 fb_div, u32 frac_fb_div, u32 post_div, int bpc, bool ss_enabled, struct radeon_atom_ss *ss) argument
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H A Dradeon_rv770_dpm.c338 reference_divider = dividers->ref_div;
419 if ((dividers.ref_div < 1) || (dividers.ref_div > 5))
437 mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]);
465 mpll_dq_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]);
515 reference_divider = 1 + dividers.ref_div;
531 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
815 (MPLL_LOCK_TIME(R600_MPLLLOCKTIME_DFLT * pi->ref_div) |
2381 pi->ref_div = dividers.ref_div
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H A Drv770_dpm.h117 u32 ref_div; member in struct:rv7xx_power_info
H A Dradeon_rv6xx_dpm.c535 (dividers->ref_div + 1);
572 (ref_clk / (dividers.ref_div + 1)),
578 (ref_clk / (dividers.ref_div + 1)));
611 rv6xx_memory_clock_entry_set_reference_divider(rdev, entry, dividers.ref_div);
690 (ref_clk / (dividers.ref_div + 1)),
696 (ref_clk / (dividers.ref_div + 1)));
1965 pi->spll_ref_div = dividers.ref_div + 1;
1972 pi->mpll_ref_div = dividers.ref_div + 1;
H A Dradeon_legacy_crtc.c271 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, argument
276 if (!ref_div)
279 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
H A Dradeon_cypress_dpm.c525 mpll_ad_func_cntl |= CLKR(dividers.ref_div);
542 mpll_dq_func_cntl |= CLKR(dividers.ref_div);
566 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
2064 pi->ref_div = dividers.ref_div + 1;
2066 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
H A Dradeon_ni_dpm.c2026 reference_divider = 1 + dividers.ref_div;
2034 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
2206 mpll_ad_func_cntl |= CLKR(dividers.ref_div);
2223 mpll_dq_func_cntl |= CLKR(dividers.ref_div);
2247 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
4112 pi->ref_div = dividers.ref_div + 1;
4114 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
H A Dradeon_mode.h596 u32 ref_div; member in struct:atom_clock_dividers
H A Dradeon_r600.c212 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; local
235 ref_div = 34;
237 ref_div = 4;
240 ref_div + 1, 0xFFF, 2, 30, ~0,
265 UPLL_REF_DIV(ref_div),
H A Dradeon_atombios.c2872 dividers->ref_div = args.v2.ucAction;
2892 dividers->ref_div = args.v3.ucRefDiv;
2912 dividers->ref_div = args.v5.ucRefDiv;
2937 dividers->ref_div = args.v6_out.ucPllRefDiv;
H A Dradeon_btc_dpm.c2615 pi->ref_div = dividers.ref_div + 1;
2617 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Damdgpu_dcn20_hubbub.c543 uint32_t ref_div = 0; local
546 REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div,
550 if (ref_div == 2)
/netbsd-current/sys/dev/pci/
H A Dmachfb.c136 int ref_div; member in struct:mach64_softc
577 sc->ref_div = regrb_pll(sc, PLL_REF_DIV);
578 DPRINTF("ref_div: %d\n", sc->ref_div);
582 (sc->ref_div * 2);
584 (sc->mem_freq * sc->ref_div);
935 int ref_freq, ref_div, vclk_post_div, vclk_fb_div; local
945 ref_div = regrb_pll(sc, PLL_REF_DIV);
983 dot_clock = (2 * ref_freq * vclk_fb_div) / (ref_div * post_div);
1381 q = (clock * sc->ref_div * 10
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