/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
H A D | amdgpu_pll.c | 85 * @ref_div: resulting reference divider 92 unsigned *fb_div, unsigned *ref_div) 98 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); 99 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 103 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); 119 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) 134 unsigned ref_div_min, ref_div_max, ref_div; local 209 ref_div_max, &fb_div, &ref_div); 211 (ref_div * post_di 90 amdgpu_pll_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, unsigned fb_div_max, unsigned ref_div_max, unsigned *fb_div, unsigned *ref_div) argument [all...] |
H A D | atombios_crtc.h | 50 u32 ref_div,
|
H A D | amdgpu_atombios_crtc.c | 343 /* use recommended ref_div for ss */ 588 u32 ref_div, 615 args.v1.usRefDiv = cpu_to_le16(ref_div); 625 args.v2.usRefDiv = cpu_to_le16(ref_div); 635 args.v3.usRefDiv = cpu_to_le16(ref_div); 652 args.v5.ucRefDiv = ref_div; 682 args.v6.ucRefDiv = ref_div; 832 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; local 861 &fb_div, &frac_fb_div, &ref_div, &post_div); 868 ref_div, fb_di 582 amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, u32 encoder_mode, u32 encoder_id, u32 clock, u32 ref_div, u32 fb_div, u32 frac_fb_div, u32 post_div, int bpc, bool ss_enabled, struct amdgpu_atom_ss *ss) argument [all...] |
H A D | amdgpu_atombios.h | 45 u32 ref_div; member in struct:atom_clock_dividers
|
H A D | amdgpu_atombios.c | 1037 dividers->ref_div = args.v3.ucRefDiv; 1057 dividers->ref_div = args.v5.ucRefDiv; 1081 dividers->ref_div = args.v6_out.ucPllRefDiv;
|
H A D | si_dpm.h | 573 u32 ref_div; member in struct:rv7xx_power_info
|
/netbsd-current/sys/arch/mips/atheros/ |
H A D | ar9344.c | 123 uint32_t out_div, ref_div, nint, post_div; local 141 ref_div = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_REFDIV); 145 const uint32_t cpu_pll_freq = (nint * ref_clk / ref_div) >> out_div; 152 ref_div = __SHIFTOUT(pll, AR9344_DDR_PLL_CONFIG_REFDIV); 156 const uint32_t ddr_pll_freq = (nint * ref_clk / ref_div) >> out_div;
|
/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/ |
H A D | radeon_display.c | 917 * @ref_div: resulting reference divider 924 unsigned *fb_div, unsigned *ref_div) 930 *ref_div = min(max(den/post_div, 1u), ref_div_max); 931 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 935 *ref_div = (*ref_div * fb_div_max)/(*fb_div); 951 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) 966 unsigned ref_div_min, ref_div_max, ref_div; local 1044 ref_div_max, &fb_div, &ref_div); 1046 (ref_div * post_di 922 avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, unsigned fb_div_max, unsigned ref_div_max, unsigned *fb_div, unsigned *ref_div) argument 1169 uint32_t ref_div; local [all...] |
H A D | radeon_clocks.c | 48 uint32_t fb_div, ref_div, post_div, sclk; local 55 ref_div = 58 if (ref_div == 0) 61 sclk = fb_div / ref_div; 78 uint32_t fb_div, ref_div, post_div, mclk; local 85 ref_div = 88 if (ref_div == 0) 91 mclk = fb_div / ref_div; 361 int ref_div = spll->reference_div; local 363 if (!ref_div) [all...] |
H A D | radeon_rv740_dpm.c | 146 reference_divider = 1 + dividers.ref_div; 153 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 221 mpll_ad_func_cntl |= CLKR(dividers.ref_div); 238 mpll_dq_func_cntl |= CLKR(dividers.ref_div); 257 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
|
H A D | radeon_rs780_dpm.c | 92 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div); 459 if ((min_dividers.ref_div != max_dividers.ref_div) || 461 (max_dividers.ref_div != current_max_dividers.ref_div) || 995 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; local 999 (post_div * ref_div); 1018 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; local 1022 (post_div * ref_div);
|
H A D | radeon_rv730_dpm.c | 66 reference_divider = 1 + dividers.ref_div; 84 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 144 reference_divider = dividers.ref_div + 1; 159 mpll_func_cntl |= MPLL_REF_DIV(dividers.ref_div);
|
H A D | radeon_atombios_crtc.c | 632 /* use recommended ref_div for ss */ 834 u32 ref_div, 861 args.v1.usRefDiv = cpu_to_le16(ref_div); 871 args.v2.usRefDiv = cpu_to_le16(ref_div); 881 args.v3.usRefDiv = cpu_to_le16(ref_div); 898 args.v5.ucRefDiv = ref_div; 927 args.v6.ucRefDiv = ref_div; 1077 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; local 1109 &fb_div, &frac_fb_div, &ref_div, &post_div); 1112 &fb_div, &frac_fb_div, &ref_div, 828 atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, u32 encoder_mode, u32 encoder_id, u32 clock, u32 ref_div, u32 fb_div, u32 frac_fb_div, u32 post_div, int bpc, bool ss_enabled, struct radeon_atom_ss *ss) argument [all...] |
H A D | radeon_rv770_dpm.c | 338 reference_divider = dividers->ref_div; 419 if ((dividers.ref_div < 1) || (dividers.ref_div > 5)) 437 mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]); 465 mpll_dq_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]); 515 reference_divider = 1 + dividers.ref_div; 531 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 815 (MPLL_LOCK_TIME(R600_MPLLLOCKTIME_DFLT * pi->ref_div) | 2381 pi->ref_div = dividers.ref_div [all...] |
H A D | rv770_dpm.h | 117 u32 ref_div; member in struct:rv7xx_power_info
|
H A D | radeon_rv6xx_dpm.c | 535 (dividers->ref_div + 1); 572 (ref_clk / (dividers.ref_div + 1)), 578 (ref_clk / (dividers.ref_div + 1))); 611 rv6xx_memory_clock_entry_set_reference_divider(rdev, entry, dividers.ref_div); 690 (ref_clk / (dividers.ref_div + 1)), 696 (ref_clk / (dividers.ref_div + 1))); 1965 pi->spll_ref_div = dividers.ref_div + 1; 1972 pi->mpll_ref_div = dividers.ref_div + 1;
|
H A D | radeon_legacy_crtc.c | 271 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, argument 276 if (!ref_div) 279 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
|
H A D | radeon_cypress_dpm.c | 525 mpll_ad_func_cntl |= CLKR(dividers.ref_div); 542 mpll_dq_func_cntl |= CLKR(dividers.ref_div); 566 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div); 2064 pi->ref_div = dividers.ref_div + 1; 2066 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
|
H A D | radeon_ni_dpm.c | 2026 reference_divider = 1 + dividers.ref_div; 2034 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 2206 mpll_ad_func_cntl |= CLKR(dividers.ref_div); 2223 mpll_dq_func_cntl |= CLKR(dividers.ref_div); 2247 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div); 4112 pi->ref_div = dividers.ref_div + 1; 4114 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
|
H A D | radeon_mode.h | 596 u32 ref_div; member in struct:atom_clock_dividers
|
H A D | radeon_r600.c | 212 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; local 235 ref_div = 34; 237 ref_div = 4; 240 ref_div + 1, 0xFFF, 2, 30, ~0, 265 UPLL_REF_DIV(ref_div),
|
H A D | radeon_atombios.c | 2872 dividers->ref_div = args.v2.ucAction; 2892 dividers->ref_div = args.v3.ucRefDiv; 2912 dividers->ref_div = args.v5.ucRefDiv; 2937 dividers->ref_div = args.v6_out.ucPllRefDiv;
|
H A D | radeon_btc_dpm.c | 2615 pi->ref_div = dividers.ref_div + 1; 2617 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
|
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
H A D | amdgpu_dcn20_hubbub.c | 543 uint32_t ref_div = 0; local 546 REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div, 550 if (ref_div == 2)
|
/netbsd-current/sys/dev/pci/ |
H A D | machfb.c | 136 int ref_div; member in struct:mach64_softc 577 sc->ref_div = regrb_pll(sc, PLL_REF_DIV); 578 DPRINTF("ref_div: %d\n", sc->ref_div); 582 (sc->ref_div * 2); 584 (sc->mem_freq * sc->ref_div); 935 int ref_freq, ref_div, vclk_post_div, vclk_fb_div; local 945 ref_div = regrb_pll(sc, PLL_REF_DIV); 983 dot_clock = (2 * ref_freq * vclk_fb_div) / (ref_div * post_div); 1381 q = (clock * sc->ref_div * 10 [all...] |