Searched refs:pp_clks (Results 1 - 1 of 1) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_pp_smu.c | 256 const struct amd_pp_clocks *pp_clks,
262 if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) {
265 pp_clks->count,
270 dc_clks->num_levels = pp_clks->count;
276 DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);
277 dc_clks->clocks_in_khz[i] = pp_clks->clock[i];
282 const struct pp_clock_levels_with_latency *pp_clks,
288 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
291 pp_clks->num_levels,
296 clk_level_info->num_levels = pp_clks
255 pp_to_dc_clock_levels( const struct amd_pp_clocks *pp_clks, struct dm_pp_clock_levels *dc_clks, enum dm_pp_clock_type dc_clk_type) argument
281 pp_to_dc_clock_levels_with_latency( const struct pp_clock_levels_with_latency *pp_clks, struct dm_pp_clock_levels_with_latency *clk_level_info, enum dm_pp_clock_type dc_clk_type) argument
308 pp_to_dc_clock_levels_with_voltage( const struct pp_clock_levels_with_voltage *pp_clks, struct dm_pp_clock_levels_with_voltage *clk_level_info, enum dm_pp_clock_type dc_clk_type) argument
343 struct amd_pp_clocks pp_clks = { 0 }; local
429 struct pp_clock_levels_with_latency pp_clks = { 0 }; local
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