Lines Matching refs:pp_clks
256 const struct amd_pp_clocks *pp_clks,
262 if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) {
265 pp_clks->count,
270 dc_clks->num_levels = pp_clks->count;
276 DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);
277 dc_clks->clocks_in_khz[i] = pp_clks->clock[i];
282 const struct pp_clock_levels_with_latency *pp_clks,
288 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
291 pp_clks->num_levels,
296 clk_level_info->num_levels = pp_clks->num_levels;
302 DRM_DEBUG("DM_PPLIB:\t %d in kHz\n", pp_clks->data[i].clocks_in_khz);
303 clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
304 clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us;
309 const struct pp_clock_levels_with_voltage *pp_clks,
315 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
318 pp_clks->num_levels,
323 clk_level_info->num_levels = pp_clks->num_levels;
329 DRM_INFO("DM_PPLIB:\t %d in kHz, %d in mV\n", pp_clks->data[i].clocks_in_khz,
330 pp_clks->data[i].voltage_in_mv);
331 clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
332 clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv;
343 struct amd_pp_clocks pp_clks = { 0 };
349 dc_to_pp_clock_type(clk_type), &pp_clks)) {
357 &pp_clks)) {
363 pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
429 struct pp_clock_levels_with_latency pp_clks = { 0 };
436 &pp_clks);
442 &pp_clks))
447 pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type);