Searched refs:mmUVD_VCPU_CACHE_OFFSET1 (Results 1 - 15 of 15) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_4_0_d.h | 91 #define mmUVD_VCPU_CACHE_OFFSET1 0x3D38 macro
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| H A D | uvd_4_2_d.h | 64 #define mmUVD_VCPU_CACHE_OFFSET1 0x3d84 macro
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| H A D | uvd_6_0_d.h | 86 #define mmUVD_VCPU_CACHE_OFFSET1 0x3d84 macro
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| H A D | uvd_5_0_d.h | 70 #define mmUVD_VCPU_CACHE_OFFSET1 0x3d84 macro
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| H A D | uvd_7_0_offset.h | 182 #define mmUVD_VCPU_CACHE_OFFSET1 0x0584 macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 370 #define mmUVD_VCPU_CACHE_OFFSET1 0x0584 macro
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| H A D | vcn_2_0_0_offset.h | 620 #define mmUVD_VCPU_CACHE_OFFSET1 0x0244 macro
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| H A D | vcn_2_5_offset.h | 691 #define mmUVD_VCPU_CACHE_OFFSET1 0x0142 macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_vcn_v2_5.c | 423 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, 0);
490 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
497 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
1203 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1),
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| H A D | amdgpu_vcn_v2_0.c | 339 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
407 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
414 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
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| H A D | amdgpu_uvd_v5_0.c | 276 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
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| H A D | amdgpu_uvd_v4_2.c | 559 WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);
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| H A D | amdgpu_vcn_v1_0.c | 327 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
397 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,
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| H A D | amdgpu_uvd_v7_0.c | 693 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21));
836 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
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| H A D | amdgpu_uvd_v6_0.c | 602 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
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