Searched refs:mmUVD_UDEC_DBW_ADDR_CONFIG (Results 1 - 12 of 12) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h89 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3BD5 macro
H A Duvd_4_2_d.h38 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 macro
H A Duvd_6_0_d.h38 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 macro
H A Duvd_5_0_d.h38 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 macro
H A Duvd_7_0_offset.h66 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x03d5 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h154 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x03d5 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_uvd_v5_0.c287 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
H A Damdgpu_uvd_v4_2.c578 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
H A Damdgpu_vcn_v1_0.c342 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
418 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
H A Damdgpu_uvd_v6_0.c613 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
H A Damdgpu_uvd_v7_0.c708 WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG,
H A Damdgpu_gfx_v6_0.c1728 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);

Completed in 239 milliseconds