Searched refs:mmUVD_UDEC_DBW_ADDR_CONFIG (Results 1 - 12 of 12) sorted by relevance
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/ |
H A D | uvd_4_0_d.h | 89 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3BD5 macro
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H A D | uvd_4_2_d.h | 38 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 macro
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H A D | uvd_6_0_d.h | 38 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 macro
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H A D | uvd_5_0_d.h | 38 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 macro
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H A D | uvd_7_0_offset.h | 66 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x03d5 macro
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/ |
H A D | vcn_1_0_offset.h | 154 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x03d5 macro
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
H A D | amdgpu_uvd_v5_0.c | 287 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
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H A D | amdgpu_uvd_v4_2.c | 578 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
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H A D | amdgpu_vcn_v1_0.c | 342 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 418 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
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H A D | amdgpu_uvd_v6_0.c | 613 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
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H A D | amdgpu_uvd_v7_0.c | 708 WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG,
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H A D | amdgpu_gfx_v6_0.c | 1728 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
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