Searched refs:mmUVD_PGFSM_CONFIG (Results 1 - 11 of 11) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_4_0_d.h | 64 #define mmUVD_PGFSM_CONFIG 0x38F8 macro
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| H A D | uvd_4_2_d.h | 90 #define mmUVD_PGFSM_CONFIG 0x38f8 macro
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| H A D | uvd_6_0_d.h | 118 #define mmUVD_PGFSM_CONFIG 0x38c0 macro
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| H A D | uvd_5_0_d.h | 102 #define mmUVD_PGFSM_CONFIG 0x38c0 macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_jpeg_v2_0.c | 237 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
268 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
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| H A D | amdgpu_uvd_v4_2.c | 707 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK |
718 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK |
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| H A D | amdgpu_vcn_v1_0.c | 708 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
722 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
761 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
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| H A D | amdgpu_vcn_v2_0.c | 680 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
694 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
734 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 30 #define mmUVD_PGFSM_CONFIG 0x00c0 macro
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| H A D | vcn_2_0_0_offset.h | 382 #define mmUVD_PGFSM_CONFIG 0x0000 macro
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| H A D | vcn_2_5_offset.h | 397 #define mmUVD_PGFSM_CONFIG 0x0000 macro
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