Searched refs:mmUVD_MPC_SET_MUXB1 (Results 1 - 12 of 12) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h61 #define mmUVD_MPC_SET_MUXB1 0x3D7C macro
H A Duvd_4_2_d.h59 #define mmUVD_MPC_SET_MUXB1 0x3d7c macro
H A Duvd_6_0_d.h81 #define mmUVD_MPC_SET_MUXB1 0x3d7c macro
H A Duvd_5_0_d.h65 #define mmUVD_MPC_SET_MUXB1 0x3d7c macro
H A Duvd_7_0_offset.h172 #define mmUVD_MPC_SET_MUXB1 0x057c macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h354 #define mmUVD_MPC_SET_MUXB1 0x057c macro
H A Dvcn_2_0_0_offset.h604 #define mmUVD_MPC_SET_MUXB1 0x023c macro
H A Dvcn_2_5_offset.h769 #define mmUVD_MPC_SET_MUXB1 0x02d1 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_uvd_v5_0.c348 WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
H A Damdgpu_uvd_v4_2.c301 WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
H A Damdgpu_uvd_v6_0.c764 WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
H A Damdgpu_uvd_v7_0.c1009 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0);

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