Searched refs:mmUVD_MPC_SET_MUXA1 (Results 1 - 12 of 12) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h59 #define mmUVD_MPC_SET_MUXA1 0x3D7A macro
H A Duvd_4_2_d.h57 #define mmUVD_MPC_SET_MUXA1 0x3d7a macro
H A Duvd_6_0_d.h79 #define mmUVD_MPC_SET_MUXA1 0x3d7a macro
H A Duvd_5_0_d.h63 #define mmUVD_MPC_SET_MUXA1 0x3d7a macro
H A Duvd_7_0_offset.h168 #define mmUVD_MPC_SET_MUXA1 0x057a macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h350 #define mmUVD_MPC_SET_MUXA1 0x057a macro
H A Dvcn_2_0_0_offset.h600 #define mmUVD_MPC_SET_MUXA1 0x023a macro
H A Dvcn_2_5_offset.h765 #define mmUVD_MPC_SET_MUXA1 0x02cf macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_uvd_v5_0.c346 WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
H A Damdgpu_uvd_v4_2.c299 WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
H A Damdgpu_uvd_v6_0.c762 WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
H A Damdgpu_uvd_v7_0.c1007 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0);

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